Lines Matching defs:frs

161 	u32 frs;	/* PLL Freqency range for HSCK (post divider) */
336 	u32 frs, best_diff, best_pll, best_prd, best_fbd;
349 	frs = i - 1;
361 		u32 divisor = prd * (1 << frs);
401 	priv->frs = frs;
618 	u32 fbd, prd, frs;
629 	frs = priv->frs;
631 	dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n",
632 		clk_get_rate(priv->refclk), fbd, prd, frs);
644 		       (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0));
651 		       (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0));