Lines Matching defs:table
255 /* clock - voltage dependency table is empty table */
286 /* sclk is bigger than max sclk in the dependence table */
303 SMU72_Discrete_DpmTable *table)
309 table->VddcLevelCount = data->vddc_voltage_table.count;
310 for (count = 0; count < table->VddcLevelCount; count++) {
311 table->VddcTable[count] =
314 CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
320 SMU72_Discrete_DpmTable *table)
326 table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
328 table->VddGfxTable[count] =
331 CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
337 SMU72_Discrete_DpmTable *table)
342 table->VddciLevelCount = data->vddci_voltage_table.count;
343 for (count = 0; count < table->VddciLevelCount; count++) {
345 table->VddciTable[count] =
348 table->SmioTable1.Pattern[count].Voltage =
351 table->SmioTable1.Pattern[count].Smio =
353 table->Smio[count] |=
355 table->VddciTable[count] =
360 table->SmioMask1 = data->vddci_voltage_table.mask_low;
361 CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
367 SMU72_Discrete_DpmTable *table)
373 table->MvddLevelCount = data->mvdd_voltage_table.count;
374 for (count = 0; count < table->MvddLevelCount; count++) {
375 table->SmioTable2.Pattern[count].Voltage =
378 table->SmioTable2.Pattern[count].Smio =
380 table->Smio[count] |=
383 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
385 CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
392 SMU72_Discrete_DpmTable *table)
404 /* table is already swapped, so in order to use the value from it
407 uint32_t vddc_level_count = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
408 uint32_t vddgfx_level_count = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
411 /* We are populating vddc CAC data to BapmVddc table in split and merged mode */
414 table->BapmVddcVidLoSidd[count] =
416 table->BapmVddcVidHiSidd[count] =
418 table->BapmVddcVidHiSidd2[count] =
423 /* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
427 table->BapmVddGfxVidHiSidd2[count] =
434 table->BapmVddGfxVidLoSidd[count] =
436 table->BapmVddGfxVidHiSidd[count] =
438 table->BapmVddGfxVidHiSidd2[count] =
447 SMU72_Discrete_DpmTable *table)
451 result = tonga_populate_smc_vddc_table(hwmgr, table);
453 "can not populate VDDC voltage table to SMC",
456 result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
458 "can not populate VDDCI voltage table to SMC",
461 result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
463 "can not populate VDDGFX voltage table to SMC",
466 result = tonga_populate_smc_mvdd_table(hwmgr, table);
468 "can not populate MVDD voltage table to SMC",
471 result = tonga_populate_cac_tables(hwmgr, table);
502 struct SMU72_Discrete_DpmTable *table)
504 return tonga_populate_ulv_level(hwmgr, &table->Ulv);
507 static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
516 table->LinkLevel[i].PcieGenSpeed =
518 table->LinkLevel[i].PcieLaneCount =
520 table->LinkLevel[i].EnabledForActivity =
522 table->LinkLevel[i].SPC =
524 table->LinkLevel[i].DownThreshold =
526 table->LinkLevel[i].UpThreshold =
640 "engine clock dependency table", return result);
779 /* level count will send to smc once at init smc table and never change*/
990 "voltage dependency table",
1094 /* populate MCLK dpm table to SMU7 */
1135 /* level count will send to smc once at init smc table and never change*/
1174 SMU72_Discrete_DpmTable *table)
1189 table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1191 table->ACPILevel.MinVoltage =
1195 table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
1199 table->ACPILevel.SclkFrequency, ÷rs);
1206 table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
1207 table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1208 table->ACPILevel.DeepSleepDivId = 0;
1217 table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
1218 table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
1219 table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
1220 table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
1221 table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
1222 table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
1223 table->ACPILevel.CcPwrDynRm = 0;
1224 table->ACPILevel.CcPwrDynRm1 = 0;
1228 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1230 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
1231 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
1232 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
1233 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
1234 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
1235 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
1236 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
1237 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1238 CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1240 /* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
1241 table->MemoryACPILevel.MinVoltage =
1244 /* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
1247 table->MemoryACPILevel.MinMvdd =
1250 table->MemoryACPILevel.MinMvdd = 0;
1270 table->MemoryACPILevel.DllCntl =
1272 table->MemoryACPILevel.MclkPwrmgtCntl =
1274 table->MemoryACPILevel.MpllAdFuncCntl =
1276 table->MemoryACPILevel.MpllDqFuncCntl =
1278 table->MemoryACPILevel.MpllFuncCntl =
1280 table->MemoryACPILevel.MpllFuncCntl_1 =
1282 table->MemoryACPILevel.MpllFuncCntl_2 =
1284 table->MemoryACPILevel.MpllSs1 =
1286 table->MemoryACPILevel.MpllSs2 =
1289 table->MemoryACPILevel.EnabledForThrottle = 0;
1290 table->MemoryACPILevel.EnabledForActivity = 0;
1291 table->MemoryACPILevel.UpHyst = 0;
1292 table->MemoryACPILevel.DownHyst = 100;
1293 table->MemoryACPILevel.VoltageDownHyst = 0;
1295 table->MemoryACPILevel.ActivityLevel =
1298 table->MemoryACPILevel.StutterEnable = 0;
1299 table->MemoryACPILevel.StrobeEnable = 0;
1300 table->MemoryACPILevel.EdcReadEnable = 0;
1301 table->MemoryACPILevel.EdcWriteEnable = 0;
1302 table->MemoryACPILevel.RttEnable = 0;
1308 SMU72_Discrete_DpmTable *table)
1320 table->UvdLevelCount = (uint8_t) (mm_table->count);
1321 table->UvdBootLevel = 0;
1323 for (count = 0; count < table->UvdLevelCount; count++) {
1324 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1325 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1326 table->UvdLevel[count].MinVoltage.Vddc =
1329 table->UvdLevel[count].MinVoltage.VddGfx =
1333 table->UvdLevel[count].MinVoltage.Vddci =
1336 table->UvdLevel[count].MinVoltage.Phases = 1;
1341 table->UvdLevel[count].VclkFrequency,
1348 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1351 table->UvdLevel[count].DclkFrequency, ÷rs);
1356 table->UvdLevel[count].DclkDivider =
1359 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1360 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1368 SMU72_Discrete_DpmTable *table)
1380 table->VceLevelCount = (uint8_t) (mm_table->count);
1381 table->VceBootLevel = 0;
1383 for (count = 0; count < table->VceLevelCount; count++) {
1384 table->VceLevel[count].Frequency =
1386 table->VceLevel[count].MinVoltage.Vddc =
1389 table->VceLevel[count].MinVoltage.VddGfx =
1393 table->VceLevel[count].MinVoltage.Vddci =
1396 table->VceLevel[count].MinVoltage.Phases = 1;
1400 table->VceLevel[count].Frequency, ÷rs);
1405 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1407 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1414 SMU72_Discrete_DpmTable *table)
1425 table->AcpLevelCount = (uint8_t) (mm_table->count);
1426 table->AcpBootLevel = 0;
1428 for (count = 0; count < table->AcpLevelCount; count++) {
1429 table->AcpLevel[count].Frequency =
1431 table->AcpLevel[count].MinVoltage.Vddc =
1434 table->AcpLevel[count].MinVoltage.VddGfx =
1438 table->AcpLevel[count].MinVoltage.Vddci =
1441 table->AcpLevel[count].MinVoltage.Phases = 1;
1445 table->AcpLevel[count].Frequency, ÷rs);
1449 table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1451 CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
1523 SMU72_Discrete_DpmTable *table)
1529 table->GraphicsBootLevel = 0;
1530 table->MemoryBootLevel = 0;
1532 /* find boot level from dpm table*/
1540 "clock value in dependency table. "
1552 "engine clock value in dependency table."
1557 table->BootVoltage.Vddc =
1560 table->BootVoltage.VddGfx =
1563 table->BootVoltage.Vddci =
1566 table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
1568 CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1722 * as opposed to Data table, which is in Mhz unit.
1747 SMU72_Discrete_DpmTable *table)
1755 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1759 table->VRConfig |= config;
1767 table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
1772 table->VRConfig |= config;
1782 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1785 table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
1791 table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
1804 * This is a read-modify-write on the first byte of the ARB table.
1807 * This solution is ugly, but we never write the whole table only
2226 SMU72_Discrete_DpmTable *table = &(smu_data->smc_state_table);
2239 tonga_populate_smc_voltage_tables(hwmgr, table);
2243 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
2248 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
2251 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
2256 table->SystemFlags |= 0x40;
2259 result = tonga_populate_ulv_state(hwmgr, table);
2268 result = tonga_populate_smc_link_level(hwmgr, table);
2280 result = tonga_populate_smc_acpi_level(hwmgr, table);
2284 result = tonga_populate_smc_vce_level(hwmgr, table);
2288 result = tonga_populate_smc_acp_level(hwmgr, table);
2301 result = tonga_populate_smc_uvd_level(hwmgr, table);
2305 result = tonga_populate_smc_boot_level(hwmgr, table);
2320 table->GraphicsVoltageChangeEnable = 1;
2321 table->GraphicsThermThrottleEnable = 1;
2322 table->GraphicsInterval = 1;
2323 table->VoltageInterval = 1;
2324 table->ThermalInterval = 1;
2325 table->TemperatureLimitHigh =
2328 table->TemperatureLimitLow =
2331 table->MemoryVoltageChangeEnable = 1;
2332 table->MemoryInterval = 1;
2333 table->VoltageResponseTime = 0;
2334 table->PhaseResponseTime = 0;
2335 table->MemoryThermThrottleEnable = 1;
2350 table->PCIeBootLinkLevel = (uint8_t) (data->dpm_table.pcie_speed_table.count);
2352 table->PCIeGenInterval = 1;
2354 result = tonga_populate_vr_config(hwmgr, table);
2357 data->vr_config = table->VRConfig;
2358 table->ThermGpio = 17;
2359 table->SclkStepSize = 0x4000;
2363 table->VRHotGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
2367 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2374 table->AcDcGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
2378 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2398 table->ThermOutGpio = gpio_pin_assignment.uc_gpio_pin_bit_shift;
2400 table->ThermOutPolarity =
2404 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2411 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2417 table->ThermOutGpio = 17;
2418 table->ThermOutPolarity = 1;
2419 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2423 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2424 CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2425 CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2426 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2427 CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2428 CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2429 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2430 CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2431 CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2432 CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2438 (uint8_t *)&(table->SystemFlags),
2455 "Failed to populate initialize MC Reg table !", return result);
2593 "Failed to upload MC reg table !",
2930 static int tonga_set_s0_mc_reg_index(struct tonga_mc_reg_table *table)
2935 for (i = 0; i < table->last; i++) {
2936 table->mc_reg_address[i].s0 =
2937 tonga_check_s0_mc_reg_index(table->mc_reg_address[i].s1,
2940 table->mc_reg_address[i].s1;
2945 static int tonga_copy_vbios_smc_reg_table(const pp_atomctrl_mc_reg_table *table,
2950 PP_ASSERT_WITH_CODE((table->last <= SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE),
2951 "Invalid VramInfo table.", return -EINVAL);
2952 PP_ASSERT_WITH_CODE((table->num_entries <= MAX_AC_TIMING_ENTRIES),
2953 "Invalid VramInfo table.", return -EINVAL);
2955 for (i = 0; i < table->last; i++)
2956 ni_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
2958 ni_table->last = table->last;
2960 for (i = 0; i < table->num_entries; i++) {
2962 table->mc_reg_table_entry[i].mclk_max;
2963 for (j = 0; j < table->last; j++) {
2965 table->mc_reg_table_entry[i].mc_data[j];
2969 ni_table->num_entries = table->num_entries;
2975 struct tonga_mc_reg_table *table)
2981 for (i = 0, j = table->last; i < table->last; i++) {
2983 "Invalid VramInfo table.", return -EINVAL);
2985 switch (table->mc_reg_address[i].s1) {
2990 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_EMRS;
2991 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_EMRS_LP;
2992 for (k = 0; k < table->num_entries; k++) {
2993 table->mc_reg_table_entry[k].mc_data[j] =
2995 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
3000 "Invalid VramInfo table.", return -EINVAL);
3002 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS;
3003 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS_LP;
3004 for (k = 0; k < table->num_entries; k++) {
3005 table->mc_reg_table_entry[k].mc_data[j] =
3007 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3010 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
3016 "Invalid VramInfo table.", return -EINVAL);
3017 table->mc_reg_address[j].s1 = mmMC_PMG_AUTO_CMD;
3018 table->mc_reg_address[j].s0 = mmMC_PMG_AUTO_CMD;
3019 for (k = 0; k < table->num_entries; k++)
3020 table->mc_reg_table_entry[k].mc_data[j] =
3021 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
3029 table->mc_reg_address[j].s1 = mmMC_PMG_CMD_MRS1;
3030 table->mc_reg_address[j].s0 = mmMC_SEQ_PMG_CMD_MRS1_LP;
3031 for (k = 0; k < table->num_entries; k++) {
3032 table->mc_reg_table_entry[k].mc_data[j] =
3034 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
3045 table->last = j;
3050 static int tonga_set_valid_flag(struct tonga_mc_reg_table *table)
3054 for (i = 0; i < table->last; i++) {
3055 for (j = 1; j < table->num_entries; j++) {
3056 if (table->mc_reg_table_entry[j-1].mc_data[i] !=
3057 table->mc_reg_table_entry[j].mc_data[i]) {
3058 table->validflag |= (1<<i);
3071 pp_atomctrl_mc_reg_table *table;
3075 table = kzalloc(sizeof(pp_atomctrl_mc_reg_table), GFP_KERNEL);
3077 if (table == NULL)
3122 result = atomctrl_initialize_mc_reg_table(hwmgr, module_index, table);
3125 result = tonga_copy_vbios_smc_reg_table(table, ni_table);
3135 kfree(table);