pm/legacy-dpm/kv_dpm.c

139 						      ATOM_AVAILABLE_SCLK_LIST *table)
146 		if (table[i].ulSupportedSCLK > prev_sclk) {
148 				table[i].ulSupportedSCLK;
150 				table[i].usVoltageIndex;
151 			prev_sclk = table[i].ulSupportedSCLK;
161 					     ATOM_AVAILABLE_SCLK_LIST *table)
166 		if (table[i].ulSupportedSCLK != 0) {
167 			if (table[i].usVoltageIndex >= SUMO_MAX_NUMBER_VOLTAGES)
169 			vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
170 				table[i].usVoltageID;
171 			vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
172 				table[i].usVoltageIndex;
792 	struct amdgpu_clock_voltage_dependency_table *table =
795 	if (table && table->count) {
797 			if (table->entries[i].clk == pi->boot_pl.sclk)
804 		struct sumo_sclk_voltage_mapping_table *table =
807 		if (table->num_max_dpm_entries == 0)
811 			if (table->entries[i].sclk_frequency == pi->boot_pl.sclk)
894 	struct amdgpu_uvd_clock_voltage_dependency_table *table =
900 	if (table == NULL || table->count == 0)
904 	for (i = 0; i < table->count; i++) {
906 		    (pi->high_voltage_t < table->entries[i].v))
909 		pi->uvd_level[i].VclkFrequency = cpu_to_be32(table->entries[i].vclk);
910 		pi->uvd_level[i].DclkFrequency = cpu_to_be32(table->entries[i].dclk);
911 		pi->uvd_level[i].MinVddNb = cpu_to_be16(table->entries[i].v);
914 			(u8)kv_get_clk_bypass(adev, table->entries[i].vclk);
916 			(u8)kv_get_clk_bypass(adev, table->entries[i].dclk);
919 							 table->entries[i].vclk, false, &dividers);
925 							 table->entries[i].dclk, false, &dividers);
967 	struct amdgpu_vce_clock_voltage_dependency_table *table =
971 	if (table == NULL || table->count == 0)
975 	for (i = 0; i < table->count; i++) {
977 		    pi->high_voltage_t < table->entries[i].v)
980 		pi->vce_level[i].Frequency = cpu_to_be32(table->entries[i].evclk);
981 		pi->vce_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
984 			(u8)kv_get_clk_bypass(adev, table->entries[i].evclk);
987 							 table->entries[i].evclk, false, &dividers);
1028 	struct amdgpu_clock_voltage_dependency_table *table =
1034 	if (table == NULL || table->count == 0)
1038 	for (i = 0; i < table->count; i++) {
1040 		    pi->high_voltage_t < table->entries[i].v)
1043 		pi->samu_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1044 		pi->samu_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1047 			(u8)kv_get_clk_bypass(adev, table->entries[i].clk);
1050 							 table->entries[i].clk, false, &dividers);
1094 	struct amdgpu_clock_voltage_dependency_table *table =
1100 	if (table == NULL || table->count == 0)
1104 	for (i = 0; i < table->count; i++) {
1105 		pi->acp_level[i].Frequency = cpu_to_be32(table->entries[i].clk);
1106 		pi->acp_level[i].MinVoltage = cpu_to_be16(table->entries[i].v);
1109 							 table->entries[i].clk, false, &dividers);
1153 	struct amdgpu_clock_voltage_dependency_table *table =
1156 	if (table && table->count) {
1159 				if (kv_get_clock_difference(table->entries[i].clk, 40000) < 200)
1161 				else if (kv_get_clock_difference(table->entries[i].clk, 30000) < 200)
1163 				else if (kv_get_clock_difference(table->entries[i].clk, 26600) < 200)
1165 				else if (kv_get_clock_difference(table->entries[i].clk, 20000) < 200)
1167 				else if (kv_get_clock_difference(table->entries[i].clk, 10000) < 200)
1176 		struct sumo_sclk_voltage_mapping_table *table =
1180 				if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200)
1182 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200)
1184 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200)
1186 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200)
1188 				else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200)
1502 	struct amdgpu_uvd_clock_voltage_dependency_table *table =
1508 		if (table->count)
1509 			pi->uvd_boot_level = table->count - 1;
1538 	struct amdgpu_vce_clock_voltage_dependency_table *table =
1541 	for (i = 0; i < table->count; i++) {
1542 		if (table->entries[i].evclk >= evclk)
1554 	struct amdgpu_vce_clock_voltage_dependency_table *table =
1560 			pi->vce_boot_level = table->count - 1;
1588 	struct amdgpu_clock_voltage_dependency_table *table =
1594 			pi->samu_boot_level = table->count - 1;
1640 	struct amdgpu_clock_voltage_dependency_table *table =
1646 			pi->acp_boot_level = table->count - 1;
1769 	struct amdgpu_clock_voltage_dependency_table *table =
1772 	if (table && table->count) {
1774 			if ((table->entries[i].clk >= new_ps->levels[0].sclk) ||
1782 			if (table->entries[i].clk <= new_ps->levels[new_ps->num_levels - 1].sclk)
1788 			if ((new_ps->levels[0].sclk - table->entries[pi->highest_valid].clk) >
1789 			    (table->entries[pi->lowest_valid].clk - new_ps->levels[new_ps->num_levels - 1].sclk))
1795 		struct sumo_sclk_voltage_mapping_table *table =
1799 			if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk ||
1807 			if (table->entries[i].sclk_frequency <=
1815 			     table->entries[pi->highest_valid].sclk_frequency) >
1816 			    (table->entries[pi->lowest_valid].sclk_frequency -
2027 						struct amdgpu_clock_and_voltage_limits *table)
2033 		table->sclk =
2035 		table->vddc =
2040 	table->mclk = pi->sys_info.nbp_memory_clock[0];
2165 	struct amdgpu_clock_voltage_dependency_table *table =
2169 	if (table && table->count) {
2170 		for (i = table->count - 1; i >= 0; i--) {
2172 			    (kv_convert_8bit_index_to_voltage(adev, table->entries[i].v) <=
2179 		struct sumo_sclk_voltage_mapping_table *table =
2182 		for (i = table->num_max_dpm_entries - 1; i >= 0; i--) {
2184 			    (kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit) <=
2206 	struct amdgpu_clock_voltage_dependency_table *table =
2226 		for (i = table->count - 1; i >= 0; i--) {
2227 			if (stable_p_state_sclk >= table->entries[i].clk) {
2228 				stable_p_state_sclk = table->entries[i].clk;
2234 			stable_p_state_sclk = table->entries[0].clk;
2251 	if (table && table->count) {
2257 				ps->levels[i].sclk = table->entries[limit].clk;
2261 		struct sumo_sclk_voltage_mapping_table *table =
2269 				ps->levels[i].sclk = table->entries[limit].sclk_frequency;
2410 	struct amdgpu_clock_voltage_dependency_table *table =
2413 	if (table && table->count) {
2417 		for (i = 0; i < table->count; i++) {
2420 			     kv_convert_8bit_index_to_voltage(adev, table->entries[i].v)))
2423 			kv_set_divider_value(adev, i, table->entries[i].clk);
2426 							   table->entries[i].v);
2433 		struct sumo_sclk_voltage_mapping_table *table =
2437 		for (i = 0; i < table->num_max_dpm_entries; i++) {
2440 			    kv_convert_2bit_index_to_voltage(adev, table->entries[i].vid_2bit))
2443 			kv_set_divider_value(adev, i, table->entries[i].sclk_frequency);
2444 			kv_set_vid(adev, i, table->entries[i].vid_2bit);
2566 			drm_err(adev_to_drm(adev), "Unsupported IGP table: %d %d\n", frev, crev);