Lines Matching refs:amdgpu_device

305 	struct amdgpu_device *adev;
394 int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors sensor,
397 int amdgpu_dpm_get_apu_thermal_limit(struct amdgpu_device *adev, uint32_t *limit);
398 int amdgpu_dpm_set_apu_thermal_limit(struct amdgpu_device *adev, uint32_t limit);
400 int amdgpu_dpm_set_powergating_by_smu(struct amdgpu_device *adev,
403 extern int amdgpu_dpm_get_sclk(struct amdgpu_device *adev, bool low);
405 extern int amdgpu_dpm_get_mclk(struct amdgpu_device *adev, bool low);
407 int amdgpu_dpm_set_xgmi_pstate(struct amdgpu_device *adev,
410 int amdgpu_dpm_switch_power_profile(struct amdgpu_device *adev,
413 int amdgpu_dpm_pause_power_profile(struct amdgpu_device *adev,
416 int amdgpu_dpm_baco_reset(struct amdgpu_device *adev);
418 int amdgpu_dpm_mode2_reset(struct amdgpu_device *adev);
419 int amdgpu_dpm_link_reset(struct amdgpu_device *adev);
420 int amdgpu_dpm_enable_gfx_features(struct amdgpu_device *adev);
422 int amdgpu_dpm_is_baco_supported(struct amdgpu_device *adev);
424 bool amdgpu_dpm_is_mode1_reset_supported(struct amdgpu_device *adev);
425 bool amdgpu_dpm_is_link_reset_supported(struct amdgpu_device *adev);
426 int amdgpu_dpm_mode1_reset(struct amdgpu_device *adev);
428 int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
431 int amdgpu_dpm_notify_rlc_state(struct amdgpu_device *adev, bool en);
433 int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev);
435 int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
437 int amdgpu_dpm_baco_enter(struct amdgpu_device *adev);
439 int amdgpu_dpm_set_df_cstate(struct amdgpu_device *adev,
442 int amdgpu_dpm_enable_mgpu_fan_boost(struct amdgpu_device *adev);
444 int amdgpu_dpm_set_clockgating_by_smu(struct amdgpu_device *adev,
447 int amdgpu_dpm_smu_i2c_bus_access(struct amdgpu_device *adev,
450 void amdgpu_pm_acpi_event_handler(struct amdgpu_device *adev);
452 void amdgpu_dpm_compute_clocks(struct amdgpu_device *adev);
453 void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable);
454 void amdgpu_dpm_enable_vcn(struct amdgpu_device *adev, bool enable, int inst);
455 void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable);
456 void amdgpu_dpm_enable_jpeg(struct amdgpu_device *adev, bool enable);
457 void amdgpu_dpm_enable_vpe(struct amdgpu_device *adev, bool enable);
458 int amdgpu_pm_load_smu_firmware(struct amdgpu_device *adev, uint32_t *smu_version);
459 int amdgpu_dpm_handle_passthrough_sbr(struct amdgpu_device *adev, bool enable);
460 int amdgpu_dpm_send_hbm_bad_pages_num(struct amdgpu_device *adev, uint32_t size);
461 int amdgpu_dpm_send_hbm_bad_channel_flag(struct amdgpu_device *adev, uint32_t size);
462 int amdgpu_dpm_send_rma_reason(struct amdgpu_device *adev);
463 int amdgpu_dpm_get_dpm_freq_range(struct amdgpu_device *adev,
467 int amdgpu_dpm_set_soft_freq_range(struct amdgpu_device *adev,
471 int amdgpu_dpm_write_watermarks_table(struct amdgpu_device *adev);
472 int amdgpu_dpm_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
474 int amdgpu_dpm_get_residency_gfxoff(struct amdgpu_device *adev, u32 *value);
475 int amdgpu_dpm_set_residency_gfxoff(struct amdgpu_device *adev, bool value);
476 int amdgpu_dpm_get_entrycount_gfxoff(struct amdgpu_device *adev, u64 *value);
477 int amdgpu_dpm_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value);
478 uint64_t amdgpu_dpm_get_thermal_throttling_counter(struct amdgpu_device *adev);
479 void amdgpu_dpm_gfx_state_change(struct amdgpu_device *adev,
481 int amdgpu_dpm_get_ecc_info(struct amdgpu_device *adev,
483 struct amd_vce_state *amdgpu_dpm_get_vce_clock_state(struct amdgpu_device *adev,
485 void amdgpu_dpm_get_current_power_state(struct amdgpu_device *adev, enum amd_pm_state_type *state);
486 void amdgpu_dpm_set_power_state(struct amdgpu_device *adev,
488 enum amd_dpm_forced_level amdgpu_dpm_get_performance_level(struct amdgpu_device *adev);
489 int amdgpu_dpm_force_performance_level(struct amdgpu_device *adev,
491 int amdgpu_dpm_get_pp_num_states(struct amdgpu_device *adev,
493 int amdgpu_dpm_dispatch_task(struct amdgpu_device *adev,
496 int amdgpu_dpm_get_pp_table(struct amdgpu_device *adev, char **table);
497 int amdgpu_dpm_set_fine_grain_clk_vol(struct amdgpu_device *adev,
501 int amdgpu_dpm_odn_edit_dpm_table(struct amdgpu_device *adev,
505 int amdgpu_dpm_print_clock_levels(struct amdgpu_device *adev,
508 int amdgpu_dpm_emit_clock_levels(struct amdgpu_device *adev,
512 int amdgpu_dpm_set_ppfeature_status(struct amdgpu_device *adev,
514 int amdgpu_dpm_get_ppfeature_status(struct amdgpu_device *adev, char *buf);
515 int amdgpu_dpm_force_clock_level(struct amdgpu_device *adev,
518 int amdgpu_dpm_get_sclk_od(struct amdgpu_device *adev);
519 int amdgpu_dpm_set_sclk_od(struct amdgpu_device *adev, uint32_t value);
520 int amdgpu_dpm_get_mclk_od(struct amdgpu_device *adev);
521 int amdgpu_dpm_set_mclk_od(struct amdgpu_device *adev, uint32_t value);
522 int amdgpu_dpm_get_power_profile_mode(struct amdgpu_device *adev,
524 int amdgpu_dpm_set_power_profile_mode(struct amdgpu_device *adev,
526 int amdgpu_dpm_get_gpu_metrics(struct amdgpu_device *adev, void **table);
527 ssize_t amdgpu_dpm_get_xcp_metrics(struct amdgpu_device *adev, int xcp_id,
538 ssize_t amdgpu_dpm_get_pm_metrics(struct amdgpu_device *adev, void *pm_metrics,
541 int amdgpu_dpm_get_fan_control_mode(struct amdgpu_device *adev,
543 int amdgpu_dpm_set_fan_speed_pwm(struct amdgpu_device *adev,
545 int amdgpu_dpm_get_fan_speed_pwm(struct amdgpu_device *adev,
547 int amdgpu_dpm_get_fan_speed_rpm(struct amdgpu_device *adev,
549 int amdgpu_dpm_set_fan_speed_rpm(struct amdgpu_device *adev,
551 int amdgpu_dpm_set_fan_control_mode(struct amdgpu_device *adev,
553 int amdgpu_dpm_get_power_limit(struct amdgpu_device *adev,
557 int amdgpu_dpm_set_power_limit(struct amdgpu_device *adev,
559 int amdgpu_dpm_is_cclk_dpm_supported(struct amdgpu_device *adev);
560 int amdgpu_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
562 int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev,
565 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev);
566 int amdgpu_dpm_is_overdrive_enabled(struct amdgpu_device *adev);
567 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
570 int amdgpu_dpm_get_num_cpu_cores(struct amdgpu_device *adev);
571 void amdgpu_dpm_stb_debug_fs_init(struct amdgpu_device *adev);
572 int amdgpu_dpm_display_configuration_change(struct amdgpu_device *adev,
574 int amdgpu_dpm_get_clock_by_type(struct amdgpu_device *adev,
577 int amdgpu_dpm_get_display_mode_validation_clks(struct amdgpu_device *adev,
579 int amdgpu_dpm_get_clock_by_type_with_latency(struct amdgpu_device *adev,
582 int amdgpu_dpm_get_clock_by_type_with_voltage(struct amdgpu_device *adev,
585 int amdgpu_dpm_set_watermarks_for_clocks_ranges(struct amdgpu_device *adev,
587 int amdgpu_dpm_display_clock_voltage_request(struct amdgpu_device *adev,
589 int amdgpu_dpm_get_current_clocks(struct amdgpu_device *adev,
591 void amdgpu_dpm_notify_smu_enable_pwe(struct amdgpu_device *adev);
592 int amdgpu_dpm_set_active_display_count(struct amdgpu_device *adev,
594 int amdgpu_dpm_set_min_deep_sleep_dcefclk(struct amdgpu_device *adev,
596 void amdgpu_dpm_set_hard_min_dcefclk_by_freq(struct amdgpu_device *adev,
598 void amdgpu_dpm_set_hard_min_fclk_by_freq(struct amdgpu_device *adev,
600 int amdgpu_dpm_display_disable_memory_clock_switch(struct amdgpu_device *adev,
602 int amdgpu_dpm_get_max_sustainable_clocks_by_dc(struct amdgpu_device *adev,
604 enum pp_smu_status amdgpu_dpm_get_uclk_dpm_states(struct amdgpu_device *adev,
607 int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev,
609 int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type,
611 ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev,
613 int amdgpu_dpm_reset_sdma(struct amdgpu_device *adev, uint32_t inst_mask);
614 bool amdgpu_dpm_reset_sdma_is_supported(struct amdgpu_device *adev);
615 int amdgpu_dpm_reset_vcn(struct amdgpu_device *adev, uint32_t inst_mask);