Lines Matching refs:uint8_t
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
236 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
237 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
246 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
449 uint8_t h_border;
450 uint8_t v_border;
452 uint8_t atom_mode_id;
453 uint8_t refreshrate;
492 uint8_t mem_module_id;
493 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
494 uint8_t reserved1[2];
531 uint8_t mem_module_id;
532 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
533 uint8_t reserved1[2];
536 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
537 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
538 uint8_t board_i2c_feature_slave_addr;
539 uint8_t reserved3;
559 uint8_t mem_module_id;
560 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
561 uint8_t reserved1[2];
564 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
565 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
566 uint8_t board_i2c_feature_slave_addr;
567 uint8_t reserved3;
587 uint8_t mem_module_id;
588 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
589 uint8_t reserved1[2];
592 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
593 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
594 uint8_t board_i2c_feature_slave_addr;
595 uint8_t ras_rom_i2c_slave_addr;
622 uint8_t mem_module_id;
623 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
624 uint8_t hw_blt_mode; //0:HW_BLT_DMA_PIO_MODE; 1:HW_BLT_LITE_SDMA_MODE; 2:HW_BLT_PCI_IO_MODE
625 uint8_t reserved1;
628 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def
629 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id
630 uint8_t board_i2c_feature_slave_addr;
631 uint8_t ras_rom_i2c_slave_addr;
662 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
663 uint8_t pwr_on_de_to_vary_bl;
664 uint8_t pwr_down_vary_bloff_to_de;
665 uint8_t pwr_down_de_to_digoff;
666 uint8_t pwr_off_delay;
667 uint8_t pwr_on_vary_bl_to_blon;
668 uint8_t pwr_down_bloff_to_vary_bloff;
669 uint8_t panel_bpc;
670 uint8_t dpcd_edp_config_cap;
671 uint8_t dpcd_max_link_rate;
672 uint8_t dpcd_max_lane_count;
673 uint8_t dpcd_max_downspread;
674 uint8_t min_allowed_bl_level;
675 uint8_t max_allowed_bl_level;
676 uint8_t bootup_bl_level;
677 uint8_t dplvdsrxid;
704 uint8_t gpio_bitshift;
705 uint8_t gpio_mask_bitshift;
706 uint8_t gpio_id;
707 uint8_t reserved;
826 uint8_t record_type; //An emun to indicate the record type
827 uint8_t record_size; //The size of the whole record in byte
833 uint8_t i2c_id;
834 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
840 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
841 uint8_t plugin_pin_state;
893 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
894 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
900 uint8_t flag; // Future expnadibility
901 uint8_t number_of_pins; // Number of GPIO pins used to control the object
939 uint8_t hpd_pin_map[8];
945 uint8_t aux_ddc_map[8];
952 uint8_t maxtmdsclkrate_in2_5mhz;
953 uint8_t reserved;
959 uint8_t connector_type;
960 uint8_t position;
976 uint8_t bracketlen;
977 uint8_t bracketwidth;
978 uint8_t conn_num;
979 uint8_t reserved;
985 uint8_t bracketlen; //Bracket Length in mm
986 uint8_t bracketwidth; //Bracket Width in mm
987 uint8_t conn_num; //Connector numbering
988 uint8_t mini_type; //Mini Type (0 = Normal; 1 = Mini)
989 uint8_t reserved1;
990 uint8_t reserved2;
1019 uint8_t priority_id;
1020 uint8_t reserved;
1040 uint8_t number_of_path;
1041 uint8_t reserved;
1048 uint8_t number_of_path;
1049 uint8_t reserved;
1073 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1074 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1075 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1076 uint8_t ss_reserved;
1077 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
1078 uint8_t reserved1[3];
1081 uint8_t dceip_min_ver;
1082 uint8_t dceip_max_ver;
1083 uint8_t max_disp_pipe_num;
1084 uint8_t max_vbios_active_disp_pipe_num;
1085 uint8_t max_ppll_num;
1086 uint8_t max_disp_phy_num;
1087 uint8_t max_aux_pairs;
1088 uint8_t remotedisplayconfig;
1089 uint8_t reserved3[8];
1105 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1106 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1107 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1108 uint8_t ss_reserved;
1109 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1110 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1111 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1112 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1115 uint8_t dcnip_min_ver;
1116 uint8_t dcnip_max_ver;
1117 uint8_t max_disp_pipe_num;
1118 uint8_t max_vbios_active_disp_pipe_num;
1119 uint8_t max_ppll_num;
1120 uint8_t max_disp_phy_num;
1121 uint8_t max_aux_pairs;
1122 uint8_t remotedisplayconfig;
1123 uint8_t reserved3[8];
1139 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1140 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1141 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1142 uint8_t ss_reserved;
1143 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1144 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1145 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1146 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1149 uint8_t dcnip_min_ver;
1150 uint8_t dcnip_max_ver;
1151 uint8_t max_disp_pipe_num;
1152 uint8_t max_vbios_active_disp_pipe_num;
1153 uint8_t max_ppll_num;
1154 uint8_t max_disp_phy_num;
1155 uint8_t max_aux_pairs;
1156 uint8_t remotedisplayconfig;
1157 uint8_t reserved3[8];
1172 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1173 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1174 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1175 uint8_t ss_reserved;
1176 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
1177 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
1178 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1179 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
1182 uint8_t dcnip_min_ver;
1183 uint8_t dcnip_max_ver;
1184 uint8_t max_disp_pipe_num;
1185 uint8_t max_vbios_active_disp_pipum;
1186 uint8_t max_ppll_num;
1187 uint8_t max_disp_phy_num;
1188 uint8_t max_aux_pairs;
1189 uint8_t remotedisplayconfig;
1239 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
1240 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
1241 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
1242 uint8_t ss_reserved;
1244 uint8_t dfp_hardcode_mode_num;
1246 uint8_t dfp_hardcode_refreshrate;
1248 uint8_t vga_hardcode_mode_num;
1250 uint8_t vga_hardcode_refreshrate;
1253 uint8_t dcnip_min_ver;
1254 uint8_t dcnip_max_ver;
1255 uint8_t max_disp_pipe_num;
1256 uint8_t max_vbios_active_disp_pipe_num;
1257 uint8_t max_ppll_num;
1258 uint8_t max_disp_phy_num;
1259 uint8_t max_aux_pairs;
1260 uint8_t remotedisplayconfig;
1293 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
1294 uint8_t hpdlut_index; //An index into external HPD pin LUT
1296 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
1297 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
1320 uint8_t guid[16]; // a GUID is a 16 byte long string
1322 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
1323 uint8_t stereopinid; // use for eDP panel
1324 uint8_t remotedisplayconfig;
1325 uint8_t edptolvdsrxid;
1326 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
1327 uint8_t reserved[3]; // for potential expansion
1338 uint8_t profile_id; // SENSOR_PROFILES
1349 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
1350 uint8_t module_name[8];
1356 uint8_t flashlight_id; // 0: Rear, 1: Front
1357 uint8_t name[8];
1373 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1374 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1376 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1377 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1378 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
1379 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
1383 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1385 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
1386 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
1390 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1391 uint8_t version;
1406 uint8_t sym_clk;
1407 uint8_t dig_mode;
1408 uint8_t phy_sel;
1410 uint8_t common_seldeemph60__deemph_6db_4_val;
1411 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1412 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1413 uint8_t margin_deemph_lane0__deemph_sel_val;
1419 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
1420 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1421 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1422 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1423 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1424 uint8_t reserved1;
1425 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1426 uint8_t reserved2;
1430 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
1431 uint8_t tx_eq_main; // map to RDPCSTX_PHY_FUSE0/1/2/3[5:0](EQ_MAIN)
1432 uint8_t tx_eq_pre; // map to RDPCSTX_PHY_FUSE0/1/2/3[11:6](EQ_PRE)
1433 uint8_t tx_eq_post; // map to RDPCSTX_PHY_FUSE0/1/2/3[17:12](EQ_POST)
1434 uint8_t tx_vboost_lvl; // tx_vboost_lvl, map to RDPCSTX_PHY_CNTL0.RDPCS_PHY_TX_VBOOST_LVL
1438 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
1439 uint8_t version;
1446 uint8_t ucI2cRegIndex;
1447 uint8_t ucI2cRegVal;
1451 uint8_t HdmiSlvAddr;
1452 uint8_t HdmiRegNum;
1453 uint8_t Hdmi6GRegNum;
1476 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1477 uint8_t umachannelnumber; // number of memory channels
1478 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1479 uint8_t pwr_on_de_to_vary_bl;
1480 uint8_t pwr_down_vary_bloff_to_de;
1481 uint8_t pwr_down_de_to_digoff;
1482 uint8_t pwr_off_delay;
1483 uint8_t pwr_on_vary_bl_to_blon;
1484 uint8_t pwr_down_bloff_to_vary_bloff;
1485 uint8_t min_allowed_bl_level;
1486 uint8_t htc_hyst_limit;
1487 uint8_t htc_tmp_limit;
1488 uint8_t reserved1;
1489 uint8_t reserved2;
1525 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1526 uint8_t umachannelnumber; // number of memory channels
1527 uint8_t pwr_on_digon_to_de; // all pwr sequence numbers below are in uint of 4ms //
1528 uint8_t pwr_on_de_to_vary_bl;
1529 uint8_t pwr_down_vary_bloff_to_de;
1530 uint8_t pwr_down_de_to_digoff;
1531 uint8_t pwr_off_delay;
1532 uint8_t pwr_on_vary_bl_to_blon;
1533 uint8_t pwr_down_bloff_to_vary_bloff;
1534 uint8_t min_allowed_bl_level;
1535 uint8_t htc_hyst_limit;
1536 uint8_t htc_tmp_limit;
1537 uint8_t reserved1;
1538 uint8_t reserved2;
1564 uint8_t edp_pwr_on_off_delay;
1565 uint8_t edp_pwr_on_vary_bl_to_blon;
1566 uint8_t edp_pwr_down_bloff_to_vary_bloff;
1567 uint8_t edp_panel_bpc;
1568 uint8_t edp_bootup_bl_level;
1569 uint8_t reserved3[3];
1583 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1584 uint8_t umachannelnumber; // number of memory channels
1585 uint8_t htc_hyst_limit;
1586 uint8_t htc_tmp_limit;
1587 uint8_t reserved1;
1588 uint8_t reserved2;
1614 uint8_t display_signal_type;
1615 uint8_t phy_sel;
1616 uint8_t preset_level;
1617 uint8_t reserved1;
1620 uint8_t tx_vboost_level;
1621 uint8_t tx_vreg_v2i;
1622 uint8_t tx_vregdrv_byp;
1623 uint8_t tx_term_cntl;
1624 uint8_t tx_peak_level;
1625 uint8_t tx_slew_en;
1626 uint8_t tx_eq_pre;
1627 uint8_t tx_eq_main;
1628 uint8_t tx_eq_post;
1629 uint8_t tx_en_inv_pre;
1630 uint8_t tx_en_inv_post;
1631 uint8_t reserved3;
1652 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1653 uint8_t umachannelnumber; // number of memory channels
1654 uint8_t htc_hyst_limit;
1655 uint8_t htc_tmp_limit;
1656 uint8_t reserved1;
1657 uint8_t reserved2;
1668 uint8_t memoryCarvedGb; //memory carved out with setting
1669 uint8_t memoryRemainingGb; //memory remaining on system
1672 uint8_t Auto : 1;
1673 uint8_t Custom : 1;
1674 uint8_t Reserved : 6;
1676 uint8_t all8;
1689 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication.
1690 uint8_t umachannelnumber; // number of memory channels
1691 uint8_t htc_hyst_limit;
1692 uint8_t htc_tmp_limit;
1693 uint8_t reserved1; // dp_ss_control
1694 uint8_t gpu_package_id;
1699 uint8_t UMACarveoutVersion;
1700 uint8_t UMACarveoutIndexMax;
1701 uint8_t UMACarveoutTypeDefault;
1702 uint8_t UMACarveoutIndexDefault;
1703 uint8_t UMACarveoutType; //Auto or Custom
1704 uint8_t UMACarveoutIndex;
1706 uint8_t reserved3[110];
1792 uint8_t gfxip_min_ver;
1793 uint8_t gfxip_max_ver;
1794 uint8_t max_shader_engines;
1795 uint8_t max_tile_pipes;
1796 uint8_t max_cu_per_sh;
1797 uint8_t max_sh_per_se;
1798 uint8_t max_backends_per_se;
1799 uint8_t max_texture_channel_caches;
1812 uint8_t gfxip_min_ver;
1813 uint8_t gfxip_max_ver;
1814 uint8_t max_shader_engines;
1815 uint8_t max_tile_pipes;
1816 uint8_t max_cu_per_sh;
1817 uint8_t max_sh_per_se;
1818 uint8_t max_backends_per_se;
1819 uint8_t max_texture_channel_caches;
1828 uint8_t active_cu_per_sh;
1829 uint8_t active_rb_per_se;
1837 uint8_t gfxip_min_ver;
1838 uint8_t gfxip_max_ver;
1839 uint8_t max_shader_engines;
1840 uint8_t reserved;
1841 uint8_t max_cu_per_sh;
1842 uint8_t max_sh_per_se;
1843 uint8_t max_backends_per_se;
1844 uint8_t max_texture_channel_caches;
1853 uint8_t active_cu_per_sh;
1854 uint8_t active_rb_per_se;
1862 uint8_t gc_num_max_gs_thds;
1863 uint8_t gc_gs_table_depth;
1864 uint8_t gc_double_offchip_lds_buffer;
1865 uint8_t gc_max_scratch_slots_per_cu;
1872 uint8_t gfxip_min_ver;
1873 uint8_t gfxip_max_ver;
1874 uint8_t max_shader_engines;
1875 uint8_t reserved;
1876 uint8_t max_cu_per_sh;
1877 uint8_t max_sh_per_se;
1878 uint8_t max_backends_per_se;
1879 uint8_t max_texture_channel_caches;
1888 uint8_t active_cu_per_sh;
1889 uint8_t active_rb_per_se;
1897 uint8_t gc_num_max_gs_thds;
1898 uint8_t gc_gs_table_depth;
1899 uint8_t gc_double_offchip_lds_buffer;
1900 uint8_t gc_max_scratch_slots_per_cu;
1903 uint8_t cut_cu;
1904 uint8_t active_cu_total;
1905 uint8_t cu_reserved[2];
1907 uint8_t inactive_cu_per_se[8];
1913 uint8_t gfxip_min_ver;
1914 uint8_t gfxip_max_ver;
1915 uint8_t max_shader_engines;
1916 uint8_t max_tile_pipes;
1917 uint8_t max_cu_per_sh;
1918 uint8_t max_sh_per_se;
1919 uint8_t max_backends_per_se;
1920 uint8_t max_texture_channel_caches;
1929 uint8_t active_wgp_per_se;
1930 uint8_t active_rb_per_se;
1931 uint8_t active_se;
1932 uint8_t reserved1;
1937 uint8_t inactive_wgp[16];
1938 uint8_t inactive_rb[16];
1952 uint8_t smuip_min_ver;
1953 uint8_t smuip_max_ver;
1954 uint8_t smu_rsd1;
1955 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1961 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1962 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1963 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1964 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1965 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1966 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1967 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1968 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1973 uint8_t smuip_min_ver;
1974 uint8_t smuip_max_ver;
1975 uint8_t smu_rsd1;
1976 uint8_t gpuclk_ss_mode;
1982 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1983 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1984 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1985 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1986 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1987 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1988 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1989 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1990 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
1991 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
2006 uint8_t smuip_min_ver;
2007 uint8_t smuip_max_ver;
2008 uint8_t waflclk_ss_mode;
2009 uint8_t gpuclk_ss_mode;
2015 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
2016 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
2017 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
2018 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
2019 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
2020 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
2021 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
2022 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
2023 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
2024 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
2047 uint8_t smuip_min_ver;
2048 uint8_t smuip_max_ver;
2049 uint8_t waflclk_ss_mode;
2050 uint8_t gpuclk_ss_mode;
2058 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid
2059 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF
2104 uint8_t smuip_min_ver;
2105 uint8_t smuip_max_ver;
2106 uint8_t waflclk_ss_mode;
2107 uint8_t gpuclk_ss_mode;
2115 uint8_t pcc_gpio_bit;
2116 uint8_t pcc_gpio_polarity;
2170 uint8_t pcc_gpio_bit;
2171 uint8_t pcc_gpio_polarity;
2233 uint8_t liquid1_i2c_address;
2234 uint8_t liquid2_i2c_address;
2235 uint8_t vr_i2c_address;
2236 uint8_t plx_i2c_address;
2238 uint8_t liquid_i2c_linescl;
2239 uint8_t liquid_i2c_linesda;
2240 uint8_t vr_i2c_linescl;
2241 uint8_t vr_i2c_linesda;
2243 uint8_t plx_i2c_linescl;
2244 uint8_t plx_i2c_linesda;
2245 uint8_t vrsensorpresent;
2246 uint8_t liquidsensorpresent;
2251 uint8_t vddgfxvrmapping;
2252 uint8_t vddsocvrmapping;
2253 uint8_t vddmem0vrmapping;
2254 uint8_t vddmem1vrmapping;
2256 uint8_t gfxulvphasesheddingmask;
2257 uint8_t soculvphasesheddingmask;
2258 uint8_t padding8_v[2];
2261 uint8_t gfxoffset;
2262 uint8_t padding_telemetrygfx;
2265 uint8_t socoffset;
2266 uint8_t padding_telemetrysoc;
2269 uint8_t mem0offset;
2270 uint8_t padding_telemetrymem0;
2273 uint8_t mem1offset;
2274 uint8_t padding_telemetrymem1;
2276 uint8_t acdcgpio;
2277 uint8_t acdcpolarity;
2278 uint8_t vr0hotgpio;
2279 uint8_t vr0hotpolarity;
2281 uint8_t vr1hotgpio;
2282 uint8_t vr1hotpolarity;
2283 uint8_t padding1;
2284 uint8_t padding2;
2286 uint8_t ledpin0;
2287 uint8_t ledpin1;
2288 uint8_t ledpin2;
2289 uint8_t padding8_4;
2291 uint8_t pllgfxclkspreadenabled;
2292 uint8_t pllgfxclkspreadpercent;
2295 uint8_t uclkspreadenabled;
2296 uint8_t uclkspreadpercent;
2299 uint8_t socclkspreadenabled;
2300 uint8_t socclkspreadpercent;
2303 uint8_t acggfxclkspreadenabled;
2304 uint8_t acggfxclkspreadpercent;
2307 uint8_t Vr2_I2C_address;
2308 uint8_t padding_vr2[3];
2321 uint8_t liquid1_i2c_address;
2322 uint8_t liquid2_i2c_address;
2323 uint8_t vr_i2c_address;
2324 uint8_t plx_i2c_address;
2326 uint8_t liquid_i2c_linescl;
2327 uint8_t liquid_i2c_linesda;
2328 uint8_t vr_i2c_linescl;
2329 uint8_t vr_i2c_linesda;
2331 uint8_t plx_i2c_linescl;
2332 uint8_t plx_i2c_linesda;
2333 uint8_t vrsensorpresent;
2334 uint8_t liquidsensorpresent;
2339 uint8_t vddgfxvrmapping;
2340 uint8_t vddsocvrmapping;
2341 uint8_t vddmem0vrmapping;
2342 uint8_t vddmem1vrmapping;
2344 uint8_t gfxulvphasesheddingmask;
2345 uint8_t soculvphasesheddingmask;
2346 uint8_t externalsensorpresent;
2347 uint8_t padding8_v;
2350 uint8_t gfxoffset;
2351 uint8_t padding_telemetrygfx;
2354 uint8_t socoffset;
2355 uint8_t padding_telemetrysoc;
2358 uint8_t mem0offset;
2359 uint8_t padding_telemetrymem0;
2362 uint8_t mem1offset;
2363 uint8_t padding_telemetrymem1;
2365 uint8_t acdcgpio;
2366 uint8_t acdcpolarity;
2367 uint8_t vr0hotgpio;
2368 uint8_t vr0hotpolarity;
2370 uint8_t vr1hotgpio;
2371 uint8_t vr1hotpolarity;
2372 uint8_t padding1;
2373 uint8_t padding2;
2375 uint8_t ledpin0;
2376 uint8_t ledpin1;
2377 uint8_t ledpin2;
2378 uint8_t padding8_4;
2380 uint8_t pllgfxclkspreadenabled;
2381 uint8_t pllgfxclkspreadpercent;
2384 uint8_t uclkspreadenabled;
2385 uint8_t uclkspreadpercent;
2388 uint8_t fclkspreadenabled;
2389 uint8_t fclkspreadpercent;
2392 uint8_t fllgfxclkspreadenabled;
2393 uint8_t fllgfxclkspreadpercent;
2417 uint8_t vddgfxvrmapping;
2418 uint8_t vddsocvrmapping;
2419 uint8_t vddmem0vrmapping;
2420 uint8_t vddmem1vrmapping;
2422 uint8_t gfxulvphasesheddingmask;
2423 uint8_t soculvphasesheddingmask;
2424 uint8_t externalsensorpresent;
2425 uint8_t padding8_v;
2428 uint8_t gfxoffset;
2429 uint8_t padding_telemetrygfx;
2432 uint8_t socoffset;
2433 uint8_t padding_telemetrysoc;
2436 uint8_t mem0offset;
2437 uint8_t padding_telemetrymem0;
2440 uint8_t mem1offset;
2441 uint8_t padding_telemetrymem1;
2444 uint8_t acdcgpio;
2445 uint8_t acdcpolarity;
2446 uint8_t vr0hotgpio;
2447 uint8_t vr0hotpolarity;
2449 uint8_t vr1hotgpio;
2450 uint8_t vr1hotpolarity;
2451 uint8_t padding1;
2452 uint8_t padding2;
2455 uint8_t ledpin0;
2456 uint8_t ledpin1;
2457 uint8_t ledpin2;
2458 uint8_t padding8_4;
2461 uint8_t pllgfxclkspreadenabled;
2462 uint8_t pllgfxclkspreadpercent;
2466 uint8_t uclkspreadenabled;
2467 uint8_t uclkspreadpercent;
2471 uint8_t fclkspreadenabled;
2472 uint8_t fclkspreadpercent;
2476 uint8_t fllgfxclkspreadenabled;
2477 uint8_t fllgfxclkspreadpercent;
2523 uint8_t Enabled;
2524 uint8_t Speed;
2525 uint8_t Padding[2];
2527 uint8_t ControllerPort;
2528 uint8_t ControllerName;
2529 uint8_t ThermalThrotter;
2530 uint8_t I2cProtocol;
2544 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2545 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2546 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2547 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2549 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2550 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2551 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2552 uint8_t Padding8_V;
2556 uint8_t GfxOffset; // in Amps
2557 uint8_t Padding_TelemetryGfx;
2559 uint8_t SocOffset; // in Amps
2560 uint8_t Padding_TelemetrySoc;
2563 uint8_t Mem0Offset; // in Amps
2564 uint8_t Padding_TelemetryMem0;
2567 uint8_t Mem1Offset; // in Amps
2568 uint8_t Padding_TelemetryMem1;
2571 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2572 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2573 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2574 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2576 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2577 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2578 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2579 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2582 uint8_t LedPin0; // GPIO number for LedPin[0]
2583 uint8_t LedPin1; // GPIO number for LedPin[1]
2584 uint8_t LedPin2; // GPIO number for LedPin[2]
2585 uint8_t padding8_4;
2588 uint8_t PllGfxclkSpreadEnabled; // on or off
2589 uint8_t PllGfxclkSpreadPercent; // Q4.4
2593 uint8_t DfllGfxclkSpreadEnabled; // on or off
2594 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2598 uint8_t UclkSpreadEnabled; // on or off
2599 uint8_t UclkSpreadPercent; // Q4.4
2603 uint8_t SoclkSpreadEnabled; // on or off
2604 uint8_t SocclkSpreadPercent; // Q4.4
2627 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields
2628 uint8_t vddsocvrmapping; // use vr_mapping* bitfields
2629 uint8_t vddmemvrmapping; // use vr_mapping* bitfields
2630 uint8_t boardvrmapping; // use vr_mapping* bitfields
2632 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode
2633 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in)
2634 uint8_t padding8_v[2];
2638 uint8_t gfxoffset; // in amps
2639 uint8_t padding_telemetrygfx;
2642 uint8_t socoffset; // in amps
2643 uint8_t padding_telemetrysoc;
2646 uint8_t memoffset; // in amps
2647 uint8_t padding_telemetrymem;
2650 uint8_t boardoffset; // in amps
2651 uint8_t padding_telemetryboardinput;
2654 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event
2655 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event
2656 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event
2657 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event
2660 uint8_t pllgfxclkspreadenabled; // on or off
2661 uint8_t pllgfxclkspreadpercent; // q4.4
2665 uint8_t uclkspreadenabled; // on or off
2666 uint8_t uclkspreadpercent; // q4.4
2670 uint8_t fclkspreadenabled; // on or off
2671 uint8_t fclkspreadpercent; // q4.4
2676 uint8_t fllgfxclkspreadenabled; // on or off
2677 uint8_t fllgfxclkspreadpercent; // q4.4
2686 uint8_t drambitwidth; // for dram use only. see dram bit width type defines
2687 uint8_t paddingmem[3];
2694 uint8_t xgmilinkspeed[4];
2695 uint8_t xgmilinkwidth[4];
2715 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2716 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2717 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2718 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2720 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2721 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2722 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN)
2723 uint8_t Padding8_V;
2727 uint8_t GfxOffset; // in Amps
2728 uint8_t Padding_TelemetryGfx;
2730 uint8_t SocOffset; // in Amps
2731 uint8_t Padding_TelemetrySoc;
2734 uint8_t Mem0Offset; // in Amps
2735 uint8_t Padding_TelemetryMem0;
2738 uint8_t Mem1Offset; // in Amps
2739 uint8_t Padding_TelemetryMem1;
2742 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2743 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2744 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2745 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2747 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2748 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2749 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2750 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2753 uint8_t LedPin0; // GPIO number for LedPin[0]
2754 uint8_t LedPin1; // GPIO number for LedPin[1]
2755 uint8_t LedPin2; // GPIO number for LedPin[2]
2756 uint8_t padding8_4;
2759 uint8_t PllGfxclkSpreadEnabled; // on or off
2760 uint8_t PllGfxclkSpreadPercent; // Q4.4
2764 uint8_t DfllGfxclkSpreadEnabled; // on or off
2765 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2769 uint8_t UclkSpreadEnabled; // on or off
2770 uint8_t UclkSpreadPercent; // Q4.4
2774 uint8_t SoclkSpreadEnabled; // on or off
2775 uint8_t SocclkSpreadPercent; // Q4.4
2786 uint8_t GpioI2cScl; // Serial Clock
2787 uint8_t GpioI2cSda; // Serial Data
2791 uint8_t LedPin3; // GPIO number for LedPin[3] - PCIE GEN Speed
2792 uint8_t LedPin4; // GPIO number for LedPin[4] - PMFW Error Status
2796 uint8_t PowerLimitScalar[4]; //[PPT_THROTTLER_COUNT]
2798 uint8_t MvddUlvPhaseSheddingMask;
2799 uint8_t VddciUlvPhaseSheddingMask;
2800 uint8_t Padding8_Psi1;
2801 uint8_t Padding8_Psi2;
2808 uint8_t Enabled;
2809 uint8_t Speed;
2810 uint8_t SlaveAddress;
2811 uint8_t ControllerPort;
2812 uint8_t ControllerName;
2813 uint8_t ThermalThrotter;
2814 uint8_t I2cProtocol;
2815 uint8_t PaddingConfig;
2828 uint8_t GpioScl; // GPIO Number for SCL Line, used only for CKSVII2C1
2829 uint8_t GpioSda; // GPIO Number for SDA Line, used only for CKSVII2C1
2830 uint8_t FchUsbPdSlaveAddr; //For requesting USB PD controller S-states via FCH I2C when entering PME turn off
2831 uint8_t I2cSpare;
2834 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields
2835 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields
2836 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields
2837 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields
2839 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2840 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2841 uint8_t VddciUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2842 uint8_t MvddUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode
2846 uint8_t GfxOffset; // in Amps
2847 uint8_t Padding_TelemetryGfx;
2850 uint8_t SocOffset; // in Amps
2851 uint8_t Padding_TelemetrySoc;
2854 uint8_t Mem0Offset; // in Amps
2855 uint8_t Padding_TelemetryMem0;
2858 uint8_t Mem1Offset; // in Amps
2859 uint8_t Padding_TelemetryMem1;
2864 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching
2865 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching
2866 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2867 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2869 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2870 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2871 uint8_t GthrGpio; // GPIO pin configured for GTHR Event
2872 uint8_t GthrPolarity; // replace GPIO polarity for GTHR
2875 uint8_t LedPin0; // GPIO number for LedPin[0]
2876 uint8_t LedPin1; // GPIO number for LedPin[1]
2877 uint8_t LedPin2; // GPIO number for LedPin[2]
2878 uint8_t LedEnableMask;
2880 uint8_t LedPcie; // GPIO number for PCIE results
2881 uint8_t LedError; // GPIO number for Error Cases
2882 uint8_t LedSpare1[2];
2887 uint8_t PllGfxclkSpreadEnabled; // on or off
2888 uint8_t PllGfxclkSpreadPercent; // Q4.4
2892 uint8_t DfllGfxclkSpreadEnabled; // on or off
2893 uint8_t DfllGfxclkSpreadPercent; // Q4.4
2897 uint8_t UclkSpreadEnabled; // on or off
2898 uint8_t UclkSpreadPercent; // Q4.4
2902 uint8_t FclkSpreadEnabled; // on or off
2903 uint8_t FclkSpreadPercent; // Q4.4
2909 uint8_t DramBitWidth; // For DRAM use only. See Dram Bit width type defines
2910 uint8_t PaddingMem1[3];
2917 uint8_t XgmiLinkSpeed [4];
2918 uint8_t XgmiLinkWidth [4];
2936 uint8_t GfxOffset; // in Amps
2937 uint8_t Padding_TelemetryGfx;
2940 uint8_t SocOffset; // in Amps
2941 uint8_t Padding_TelemetrySoc;
2944 uint8_t MemOffset; // in Amps
2945 uint8_t Padding_TelemetryMem;
2948 uint8_t BoardOffset; // in Amps
2949 uint8_t Padding_TelemetryBoardInput;
2956 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event
2957 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event
2958 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event
2959 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event
2962 uint8_t UclkSpreadEnabled; // on or off
2963 uint8_t UclkSpreadPercent; // Q4.4
2967 uint8_t FclkSpreadEnabled; // on or off
2968 uint8_t FclkSpreadPercent; // Q4.4
2975 uint8_t GpioI2cScl; // Serial Clock
2976 uint8_t GpioI2cSda; // Serial Data
3011 uint8_t enable_gb_vdroop_table_cksoff;
3012 uint8_t enable_gb_vdroop_table_ckson;
3013 uint8_t enable_gb_fuse_table_cksoff;
3014 uint8_t enable_gb_fuse_table_ckson;
3016 uint8_t enable_apply_avfs_cksoff_voltage;
3017 uint8_t reserved;
3055 uint8_t enable_gb_vdroop_table_cksoff;
3056 uint8_t enable_gb_vdroop_table_ckson;
3057 uint8_t enable_gb_fuse_table_cksoff;
3058 uint8_t enable_gb_fuse_table_ckson;
3060 uint8_t enable_apply_avfs_cksoff_voltage;
3061 uint8_t reserved;
3080 uint8_t enable_acg_gb_vdroop_table;
3081 uint8_t enable_acg_gb_fuse_table;
3104 uint8_t uvdip_min_ver;
3105 uint8_t uvdip_max_ver;
3106 uint8_t vceip_min_ver;
3107 uint8_t vceip_max_ver;
3132 uint8_t umcip_min_ver;
3133 uint8_t umcip_max_ver;
3134 uint8_t vram_type; //enum of atom_dgpu_vram_type
3135 uint8_t umc_config;
3159 uint8_t umcip_min_ver;
3160 uint8_t umcip_max_ver;
3161 uint8_t vram_type; //enum of atom_dgpu_vram_type
3162 uint8_t umc_config;
3179 uint8_t umcip_min_ver;
3180 uint8_t umcip_max_ver;
3181 uint8_t vram_type; //enum of atom_dgpu_vram_type
3182 uint8_t umc_config;
3204 uint8_t umcip_min_ver;
3205 uint8_t umcip_max_ver;
3206 uint8_t vram_type;
3207 uint8_t umc_config;
3213 uint8_t channel_num;
3214 uint8_t channel_width;
3215 uint8_t channel_reserve[2];
3216 uint8_t umc_info_reserved[16];
3232 uint8_t ext_memory_id; // Current memory module ID
3233 uint8_t memory_type; // enum of atom_dgpu_vram_type
3234 uint8_t channel_num; // Number of mem. channels supported in this module
3235 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3236 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3237 uint8_t tunningset_id; // MC phy registers set per.
3238 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3239 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3240 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id
3241 uint8_t vram_rsd2; // reserved
3255 uint8_t vram_module_num; // indicate number of VRAM module
3256 uint8_t umcip_min_ver;
3257 uint8_t umcip_max_ver;
3258 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3268 uint8_t density;
3269 uint8_t tunningset_id;
3270 uint8_t ext_memory_id;
3271 uint8_t dram_vendor_id;
3290 uint8_t vram_module_num;
3291 uint8_t umcip_min_ver;
3292 uint8_t umcip_max_ver;
3293 uint8_t mc_phy_tile_num;
3294 uint8_t memory_type;
3295 uint8_t channel_num;
3296 uint8_t channel_width;
3297 uint8_t reserved1;
3355 uint8_t ext_memory_id; // Current memory module ID
3356 uint8_t memory_type; // enum of atom_dgpu_vram_type
3357 uint8_t channel_num; // Number of mem. channels supported in this module
3358 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3359 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3360 uint8_t tunningset_id; // MC phy registers set per
3361 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3362 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3363 uint8_t vram_flags; // bit0= bankgroup enable
3364 uint8_t vram_rsd2; // reserved
3382 uint8_t vram_module_num; // indicate number of VRAM module
3383 uint8_t umcip_min_ver;
3384 uint8_t umcip_max_ver;
3385 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3395 uint8_t ext_memory_id; // Current memory module ID
3396 uint8_t memory_type; // enum of atom_dgpu_vram_type
3397 uint8_t channel_num; // Number of mem. channels supported in this module
3398 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
3399 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
3400 uint8_t tunningset_id; // MC phy registers set per.
3402 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
3403 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
3404 uint8_t vram_flags; // bit0= bankgroup enable
3405 uint8_t vram_rsd2; // reserved
3418 uint8_t RL;
3419 uint8_t WL;
3420 uint8_t tRAS;
3421 uint8_t tRC;
3424 uint8_t tRFC;
3425 uint8_t tRFCpb;
3427 uint8_t tRREFD;
3428 uint8_t tRCDRD;
3429 uint8_t tRCDWR;
3430 uint8_t tRP;
3432 uint8_t tRRDS;
3433 uint8_t tRRDL;
3434 uint8_t tWR;
3435 uint8_t tWTRS;
3437 uint8_t tWTRL;
3438 uint8_t tFAW;
3439 uint8_t tCCDS;
3440 uint8_t tCCDL;
3442 uint8_t tCRCRL;
3443 uint8_t tCRCWL;
3444 uint8_t tCKE;
3445 uint8_t tCKSRE;
3447 uint8_t tCKSRX;
3448 uint8_t tRTPS;
3449 uint8_t tRTPL;
3450 uint8_t tMRD;
3452 uint8_t tMOD;
3453 uint8_t tXS;
3454 uint8_t tXHP;
3455 uint8_t tXSMRS;
3459 uint8_t tPD;
3460 uint8_t tXP;
3461 uint8_t tCPDED;
3462 uint8_t tACTPDE;
3464 uint8_t tPREPDE;
3465 uint8_t tREFPDE;
3466 uint8_t tMRSPDEN;
3467 uint8_t tRDSRE;
3469 uint8_t tWRSRE;
3470 uint8_t tPPD;
3471 uint8_t tCCDMW;
3472 uint8_t tWTRTR;
3474 uint8_t tLTLTR;
3475 uint8_t tREFTR;
3476 uint8_t VNDR;
3477 uint8_t reserved[9];
3492 uint8_t phyintf_ck_inverted[8]; //UMC_PHY_PHYINTF_CNTL.INV_CK
3506 uint8_t vram_module_num; // indicate number of VRAM module
3507 uint8_t umcip_min_ver;
3508 uint8_t umcip_max_ver;
3509 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
3523 uint8_t vram_module_num;
3524 uint8_t umcip_min_ver;
3525 uint8_t umcip_max_ver;
3526 uint8_t mc_phy_tile_num;
3541 uint8_t voltage_type; //enum atom_voltage_type
3542 uint8_t voltage_mode; //enum atom_voltage_object_mode
3560 uint8_t regulator_id; //Indicate Voltage Regulator Id
3561 uint8_t i2c_id;
3562 uint8_t i2c_slave_addr;
3563 uint8_t i2c_control_offset;
3564 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
3565 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
3566 uint8_t reserved[2];
3587 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
3588 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
3589 uint8_t phase_delay_us; // phase delay in unit of micro second
3590 uint8_t reserved;
3598 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
3599 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
3600 uint8_t psi0_enable; //
3601 uint8_t maxvstep;
3602 uint8_t telemetry_offset;
3603 uint8_t telemetry_gain;
3610 uint8_t merged_powerrail_type; //enum atom_voltage_type
3611 uint8_t reserved[3];
3756 uint8_t voltagetype; /* enum atom_voltage_type */
3757 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
3805 uint8_t pll_ss_enable;
3806 uint8_t reserved;
3821 uint8_t reserved;
3822 uint8_t bitslen;
3840 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
3841 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
3842 uint8_t command; // enum of atom_get_smu_clock_info_command
3843 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
4021 uint8_t ucode_func_id;
4022 uint8_t ucode_reserved[3];
4037 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
4038 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
4040 uint8_t encoder_mode; // Encoder mode:
4041 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
4042 uint8_t crtc_id; // enum of atom_crtc_def
4043 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
4044 uint8_t reserved1[2];
4083 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
4084 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
4085 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
4086 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
4130 uint8_t crtc_id; // enum atom_crtc_def
4131 uint8_t blanking; // enum atom_blank_crtc_command
4147 uint8_t crtc_id; // enum atom_crtc_def
4148 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
4149 uint8_t padding[2];
4158 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
4159 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
4160 uint8_t padding[2];
4183 uint8_t h_border;
4184 uint8_t v_border;
4185 uint8_t crtc_id; // enum atom_crtc_def
4186 uint8_t encoder_mode; // atom_encode_mode_def
4187 uint8_t padding[2];
4196 uint8_t i2cspeed_khz;
4198 uint8_t regindex;
4199 uint8_t status; /* enum atom_process_i2c_flag */
4202 uint8_t flag; /* enum atom_process_i2c_status */
4203 uint8_t trans_bytes;
4204 uint8_t slave_addr;
4205 uint8_t i2c_id;
4233 uint8_t channelid;
4235 uint8_t reply_status;
4236 uint8_t aux_delay;
4238 uint8_t dataout_len;
4239 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
4249 uint8_t crtc_id; // enum atom_crtc_def
4250 uint8_t encoder_id; // enum atom_dig_def
4251 uint8_t encode_mode; // enum atom_encode_mode_def
4252 uint8_t dst_bpc; // enum atom_panel_bit_per_color
4302 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4303 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
4304 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4305 uint8_t lanenum; // Lane number
4307 uint8_t bitpercolor;
4308 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
4309 uint8_t reserved[2];
4314 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4315 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
4316 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
4317 uint8_t lanenum; // Lane number
4318 uint8_t symclk_10khz; // Symbol Clock in 10Khz
4319 uint8_t hpd_sel;
4320 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4321 uint8_t reserved[2];
4326 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4327 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
4328 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
4329 uint8_t reserved1;
4335 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
4336 uint8_t action; // = rest of generic encoder command which does not carry any parameters
4337 uint8_t reserved1[2];
4356 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
4357 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
4359 uint8_t digmode; // enum atom_encode_mode_def
4360 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
4362 uint8_t lanenum; // Lane number 1, 2, 4, 8
4364 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
4365 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
4366 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
4367 uint8_t reserved;
4445 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
4446 uint8_t action; //
4447 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
4448 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
4449 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
4450 uint8_t hpd_id;
4498 uint8_t revision;
4499 uint8_t checksum;
4500 uint8_t oemId[6];
4501 uint8_t oemTableId[8]; //UINT64 OemTableId;
4509 uint8_t tableUUID[16]; //0x24
4530 uint8_t vbioscontent[1];
4535 uint8_t lib1content[1];