Lines Matching refs:packet
46 struct pm4_mes_map_process *packet;
48 packet = (struct pm4_mes_map_process *)buffer;
52 packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
54 packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
55 packet->bitfields2.process_quantum = 10;
56 packet->bitfields2.pasid = pdd->pasid;
57 packet->bitfields3.page_table_base = qpd->page_table_base;
58 packet->bitfields10.gds_size = qpd->gds_size;
59 packet->bitfields10.num_gws = qpd->num_gws;
60 packet->bitfields10.num_oac = qpd->num_oac;
61 packet->bitfields10.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
63 packet->sh_mem_config = qpd->sh_mem_config;
64 packet->sh_mem_bases = qpd->sh_mem_bases;
65 packet->sh_mem_ape1_base = qpd->sh_mem_ape1_base;
66 packet->sh_mem_ape1_limit = qpd->sh_mem_ape1_limit;
68 packet->sh_hidden_private_base_vmid = qpd->sh_hidden_private_base;
70 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
71 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
79 struct pm4_mes_runlist *packet;
98 packet = (struct pm4_mes_runlist *)buffer;
101 packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
104 packet->bitfields4.ib_size = ib_size_in_dwords;
105 packet->bitfields4.chain = chain ? 1 : 0;
106 packet->bitfields4.offload_polling = 0;
107 packet->bitfields4.valid = 1;
108 packet->bitfields4.process_cnt = concurrent_proc_cnt;
109 packet->ordinal2 = lower_32_bits(ib);
110 packet->bitfields3.ib_base_hi = upper_32_bits(ib);
118 struct pm4_mes_set_resources *packet;
120 packet = (struct pm4_mes_set_resources *)buffer;
123 packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES,
126 packet->bitfields2.queue_type =
128 packet->bitfields2.vmid_mask = res->vmid_mask;
129 packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
130 packet->bitfields7.oac_mask = res->oac_mask;
131 packet->bitfields8.gds_heap_base = res->gds_heap_base;
132 packet->bitfields8.gds_heap_size = res->gds_heap_size;
134 packet->gws_mask_lo = lower_32_bits(res->gws_mask);
135 packet->gws_mask_hi = upper_32_bits(res->gws_mask);
137 packet->queue_mask_lo = lower_32_bits(res->queue_mask);
138 packet->queue_mask_hi = upper_32_bits(res->queue_mask);
146 struct pm4_mes_map_queues *packet;
149 packet = (struct pm4_mes_map_queues *)buffer;
152 packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
154 packet->bitfields2.num_queues = 1;
155 packet->bitfields2.queue_sel =
158 packet->bitfields2.engine_sel =
160 packet->bitfields2.queue_type =
166 packet->bitfields2.queue_type =
170 packet->bitfields2.queue_type =
175 packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
183 packet->bitfields3.doorbell_offset =
186 packet->mqd_addr_lo =
189 packet->mqd_addr_hi =
192 packet->wptr_addr_lo =
195 packet->wptr_addr_hi =
205 struct pm4_mes_unmap_queues *packet;
207 packet = (struct pm4_mes_unmap_queues *)buffer;
210 packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
213 packet->bitfields2.engine_sel =
217 packet->bitfields2.action =
220 packet->bitfields2.action =
225 packet->bitfields2.queue_sel =
227 packet->bitfields3a.pasid = filter_param;
230 packet->bitfields2.queue_sel =
235 packet->bitfields2.queue_sel =
250 struct pm4_mes_query_status *packet;
252 packet = (struct pm4_mes_query_status *)buffer;
255 packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
258 packet->bitfields2.context_id = 0;
259 packet->bitfields2.interrupt_sel =
261 packet->bitfields2.command =
264 packet->addr_hi = upper_32_bits((uint64_t)fence_address);
265 packet->addr_lo = lower_32_bits((uint64_t)fence_address);
266 packet->data_hi = upper_32_bits((uint64_t)fence_value);
267 packet->data_lo = lower_32_bits((uint64_t)fence_value);
274 struct pm4_mec_release_mem *packet;
276 packet = (struct pm4_mec_release_mem *)buffer;
277 memset(buffer, 0, sizeof(*packet));
279 packet->header.u32All = pm_build_pm4_header(IT_RELEASE_MEM,
280 sizeof(*packet));
282 packet->bitfields2.event_type = CACHE_FLUSH_AND_INV_TS_EVENT;
283 packet->bitfields2.event_index = event_index___release_mem__end_of_pipe;
284 packet->bitfields2.tcl1_action_ena = 1;
285 packet->bitfields2.tc_action_ena = 1;
286 packet->bitfields2.cache_policy = cache_policy___release_mem__lru;
287 packet->bitfields2.atc = 0;
289 packet->bitfields3.data_sel = data_sel___release_mem__send_32_bit_low;
290 packet->bitfields3.int_sel =
293 packet->bitfields4.address_lo_32b = (gpu_addr & 0xffffffff) >> 2;
294 packet->address_hi = upper_32_bits(gpu_addr);
296 packet->data_lo = 0;