amd/amdkfd/kfd_packet_manager_v9.c

35 	struct pm4_mes_map_process *packet;
42 	packet = (struct pm4_mes_map_process *)buffer;
44 	packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
47 		packet->bitfields2.exec_cleaner_shader = 1;
48 	packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
49 	packet->bitfields2.process_quantum = 10;
50 	packet->bitfields2.pasid = pdd->pasid;
51 	packet->bitfields14.gds_size = qpd->gds_size & 0x3F;
52 	packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF;
53 	packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0;
54 	packet->bitfields14.num_oac = qpd->num_oac;
55 	packet->bitfields14.sdma_enable = 1;
56 	packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
60 		packet->bitfields2.debug_vmid = kfd->dqm->trap_debug_vmid;
61 		packet->bitfields2.new_debug = 1;
64 	packet->sh_mem_config = qpd->sh_mem_config;
65 	packet->sh_mem_bases = qpd->sh_mem_bases;
67 		packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
71 		packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8)
74 		packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
75 		packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
78 	packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
79 	packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
81 	packet->vm_context_page_table_base_addr_lo32 =
83 	packet->vm_context_page_table_base_addr_hi32 =
92 	struct pm4_mes_map_process_aldebaran *packet;
101 	packet = (struct pm4_mes_map_process_aldebaran *)buffer;
103 	packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS,
107 		packet->bitfields2.exec_cleaner_shader = 1;
108 	packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0;
109 	packet->bitfields2.process_quantum = 10;
110 	packet->bitfields2.pasid = pdd->pasid;
111 	packet->bitfields14.gds_size = qpd->gds_size & 0x3F;
112 	packet->bitfields14.gds_size_hi = (qpd->gds_size >> 6) & 0xF;
113 	packet->bitfields14.num_gws = (qpd->mapped_gws_queue) ? qpd->num_gws : 0;
114 	packet->bitfields14.num_oac = qpd->num_oac;
115 	packet->bitfields14.sdma_enable = 1;
116 	packet->bitfields14.num_queues = (qpd->is_debug) ? 0 : qpd->queue_count;
117 	packet->spi_gdbg_per_vmid_cntl = pdd->spi_dbg_override |
122 			packet->tcp_watch_cntl[i] = pdd->watch_points[i];
124 		packet->bitfields2.single_memops =
128 	packet->sh_mem_config = qpd->sh_mem_config;
129 	packet->sh_mem_bases = qpd->sh_mem_bases;
131 		packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8);
132 		packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8);
133 		packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8);
134 		packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8);
137 	packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area);
138 	packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area);
140 	packet->vm_context_page_table_base_addr_lo32 =
142 	packet->vm_context_page_table_base_addr_hi32 =
151 	struct pm4_mes_runlist *packet;
173 	packet = (struct pm4_mes_runlist *)buffer;
176 	packet->header.u32All = pm_build_pm4_header(IT_RUN_LIST,
179 	packet->bitfields4.ib_size = ib_size_in_dwords;
180 	packet->bitfields4.chain = chain ? 1 : 0;
181 	packet->bitfields4.offload_polling = 0;
182 	packet->bitfields4.chained_runlist_idle_disable = chain ? 1 : 0;
183 	packet->bitfields4.valid = 1;
184 	packet->bitfields4.process_cnt = concurrent_proc_cnt;
185 	packet->ordinal2 = lower_32_bits(ib);
186 	packet->ib_base_hi = upper_32_bits(ib);
194 	struct pm4_mes_set_resources *packet;
196 	packet = (struct pm4_mes_set_resources *)buffer;
199 	packet->header.u32All = pm_build_pm4_header(IT_SET_RESOURCES,
202 	packet->bitfields2.queue_type =
204 	packet->bitfields2.vmid_mask = res->vmid_mask;
205 	packet->bitfields2.unmap_latency = KFD_UNMAP_LATENCY_MS / 100;
207 		packet->bitfields2.enb_xnack_retry_disable_check = 1;
208 	packet->bitfields7.oac_mask = res->oac_mask;
209 	packet->bitfields8.gds_heap_base = res->gds_heap_base;
210 	packet->bitfields8.gds_heap_size = res->gds_heap_size;
212 	packet->gws_mask_lo = lower_32_bits(res->gws_mask);
213 	packet->gws_mask_hi = upper_32_bits(res->gws_mask);
215 	packet->queue_mask_lo = lower_32_bits(res->queue_mask);
216 	packet->queue_mask_hi = upper_32_bits(res->queue_mask);
230 	struct pm4_mes_map_queues *packet;
232 	packet = (struct pm4_mes_map_queues *)buffer;
235 	packet->header.u32All = pm_build_pm4_header(IT_MAP_QUEUES,
237 	packet->bitfields2.num_queues = 1;
238 	packet->bitfields2.queue_sel =
241 	packet->bitfields2.engine_sel =
243 	packet->bitfields2.gws_control_queue = q->properties.is_gws ? 1 : 0;
244 	packet->bitfields2.extended_engine_sel =
246 	packet->bitfields2.queue_type =
252 			packet->bitfields2.queue_type =
256 		packet->bitfields2.queue_type =
263 			packet->bitfields2.engine_sel = q->properties.sdma_engine_id +
272 				packet->bitfields2.extended_engine_sel =
275 				packet->bitfields2.extended_engine_sel =
278 			packet->bitfields2.engine_sel = q->properties.sdma_engine_id % 8;
285 	packet->bitfields3.doorbell_offset =
288 	packet->mqd_addr_lo =
291 	packet->mqd_addr_hi =
294 	packet->wptr_addr_lo =
297 	packet->wptr_addr_hi =
316 /* pm_config_dequeue_wait_counts_v9: Builds WRITE_DATA packet with
320  *  filled in with packet
328 	struct pm4_mec_write_data_mmio *packet;
377 	packet = (struct pm4_mec_write_data_mmio *)buffer;
380 	packet->header.u32All = pm_build_pm4_header(IT_WRITE_DATA,
383 	packet->bitfields2.dst_sel  = dst_sel___write_data__mem_mapped_register;
384 	packet->bitfields2.addr_incr =
387 	packet->bitfields3.dst_mmreg_addr = reg_offset;
389 	packet->data = reg_data;
398 	struct pm4_mes_unmap_queues *packet;
400 	packet = (struct pm4_mes_unmap_queues *)buffer;
403 	packet->header.u32All = pm_build_pm4_header(IT_UNMAP_QUEUES,
406 	packet->bitfields2.extended_engine_sel =
411 	packet->bitfields2.engine_sel =
415 		packet->bitfields2.action =
418 		packet->bitfields2.action =
423 		packet->bitfields2.queue_sel =
425 		packet->bitfields3a.pasid = filter_param;
428 		packet->bitfields2.queue_sel =
433 		packet->bitfields2.queue_sel =
448 	struct pm4_mes_query_status *packet;
450 	packet = (struct pm4_mes_query_status *)buffer;
454 	packet->header.u32All = pm_build_pm4_header(IT_QUERY_STATUS,
457 	packet->bitfields2.context_id = 0;
458 	packet->bitfields2.interrupt_sel =
460 	packet->bitfields2.command =
463 	packet->addr_hi = upper_32_bits((uint64_t)fence_address);
464 	packet->addr_lo = lower_32_bits((uint64_t)fence_address);
465 	packet->data_hi = upper_32_bits((uint64_t)fence_value);
466 	packet->data_lo = lower_32_bits((uint64_t)fence_value);