amd/amdgpu/vce_v3_0.c

85 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
87 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
96 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
117 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
119 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
128 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
148 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
150 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
153 		WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
155 		WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
157 		WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
159 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
185 		WREG32(mmVCE_CLOCK_GATING_B, data);
190 		WREG32(mmVCE_UENC_CLOCK_GATING, data);
195 		WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
199 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
206 		WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
211 		WREG32(mmVCE_CLOCK_GATING_B, data);
215 		WREG32(mmVCE_UENC_CLOCK_GATING, data);
219 		WREG32(mmVCE_UENC_CLOCK_GATING_2, data);
223 		WREG32(mmVCE_UENC_REG_CLOCK_GATING, data);
230 		WREG32(mmVCE_UENC_DMA_DCLK_CTRL, data);
275 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
281 			WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr));
282 			WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr));
283 			WREG32(mmVCE_RB_BASE_LO, ring->gpu_addr);
284 			WREG32(mmVCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
285 			WREG32(mmVCE_RB_SIZE, ring->ring_size / 4);
288 			WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr));
289 			WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr));
290 			WREG32(mmVCE_RB_BASE_LO2, ring->gpu_addr);
291 			WREG32(mmVCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
292 			WREG32(mmVCE_RB_SIZE2, ring->ring_size / 4);
295 			WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr));
296 			WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr));
297 			WREG32(mmVCE_RB_BASE_LO3, ring->gpu_addr);
298 			WREG32(mmVCE_RB_BASE_HI3, upper_32_bits(ring->gpu_addr));
299 			WREG32(mmVCE_RB_SIZE3, ring->ring_size / 4);
325 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
340 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(idx));
351 		WREG32(mmVCE_STATUS, 0);
354 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);
556 	WREG32(mmVCE_CLOCK_GATING_B, 0x1FF);
558 	WREG32(mmVCE_LMI_CTRL, 0x00398000);
560 	WREG32(mmVCE_LMI_SWAP_CNTL, 0);
561 	WREG32(mmVCE_LMI_SWAP_CNTL1, 0);
562 	WREG32(mmVCE_LMI_VM_CTRL, 0);
566 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR0, (adev->vce.gpu_addr >> 8));
567 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR1, (adev->vce.gpu_addr >> 8));
568 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR2, (adev->vce.gpu_addr >> 8));
570 		WREG32(mmVCE_LMI_VCPU_CACHE_40BIT_BAR, (adev->vce.gpu_addr >> 8));
573 	WREG32(mmVCE_VCPU_CACHE_OFFSET0, offset & 0x7fffffff);
574 	WREG32(mmVCE_VCPU_CACHE_SIZE0, size);
579 		WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0x7fffffff);
580 		WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
583 		WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0x7fffffff);
584 		WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
588 		WREG32(mmVCE_VCPU_CACHE_OFFSET1, offset & 0xfffffff);
589 		WREG32(mmVCE_VCPU_CACHE_SIZE1, size);
592 		WREG32(mmVCE_VCPU_CACHE_OFFSET2, offset & 0xfffffff);
593 		WREG32(mmVCE_VCPU_CACHE_SIZE2, size);
648 	WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
653 	WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(1));
658 	WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(0));
685 		WREG32(mmSRBM_SOFT_RESET, tmp);
691 		WREG32(mmSRBM_SOFT_RESET, tmp);
779 		WREG32(mmGRBM_GFX_INDEX, GET_VCE_INSTANCE(i));
786 			WREG32(mmVCE_CLOCK_GATING_A, data);
792 			WREG32(mmVCE_UENC_CLOCK_GATING, data);
798 	WREG32(mmGRBM_GFX_INDEX, mmGRBM_GFX_INDEX_DEFAULT);