amd/amdgpu/uvd_v5_0.c

88 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
286 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
288 	WREG32(mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
293 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, offset >> 3);
294 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
298 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, offset >> 3);
299 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
304 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, offset >> 3);
305 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
307 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
308 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
309 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
344 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
356 	WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
364 	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
365 	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
367 	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
368 	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
369 	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
370 	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
371 	WREG32(mmUVD_MPC_SET_ALU, 0);
372 	WREG32(mmUVD_MPC_SET_MUX, 0x88);
375 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
379 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);
385 	WREG32(mmUVD_SOFT_RESET, 0);
428 	WREG32(mmUVD_RBC_RB_CNTL, tmp);
431 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
434 	WREG32(mmUVD_RBC_RB_RPTR_ADDR, (upper_32_bits(ring->gpu_addr) >> 2));
437 	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
439 	WREG32(mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
443 	WREG32(mmUVD_RBC_RB_RPTR, 0);
446 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
463 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
470 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
474 	WREG32(mmUVD_VCPU_CNTL, 0x0);
479 	WREG32(mmUVD_STATUS, 0);
528 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
675 	WREG32(mmUVD_SUVD_CGC_GATE, data1);
676 	WREG32(mmUVD_CGC_GATE, data3);
722 	WREG32(mmUVD_CGC_CTRL, data);
723 	WREG32(mmUVD_SUVD_CGC_CTRL, data2);
762 	WREG32(mmUVD_CGC_GATE, data);
763 	WREG32(mmUVD_SUVD_CGC_GATE, data1);
780 			WREG32(mmUVD_CGC_CTRL, data);
789 			WREG32(mmUVD_CGC_CTRL, data);