amd/amdgpu/uvd_v4_2.c

90 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
296 	WREG32(mmUVD_CGC_GATE, 0);
303 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);
313 	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
314 	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
317 	WREG32(mmUVD_LMI_CTRL, 0x203108);
320 	WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
322 	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
323 	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
324 	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
325 	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
326 	WREG32(mmUVD_MPC_SET_ALU, 0);
327 	WREG32(mmUVD_MPC_SET_MUX, 0x88);
377 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
380 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
383 	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
387 	WREG32(mmUVD_RBC_RB_RPTR, 0x0);
390 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
393 	WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
415 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
458 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
462 	WREG32(mmUVD_STATUS, 0);
513 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
582 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
583 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
587 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
588 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
593 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
594 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
598 	WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
602 	WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
604 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
605 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
606 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
622 			WREG32(mmUVD_CGC_CTRL, data);
631 			WREG32(mmUVD_CGC_CTRL, data);
658 	WREG32(mmUVD_CGC_CTRL, tmp);
735 				WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |
746 				WREG32(mmUVD_PGFSM_CONFIG, (UVD_PGFSM_CONFIG__UVD_PGFSM_FSM_ADDR_MASK   |