Lines Matching refs:WREG32

76 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
146 	WREG32(mmUVD_CONTEXT_ID, 0xCAFEDEAD);
229 	WREG32(mmUVD_CGC_CTRL, tmp);
248 	WREG32(mmUVD_VCPU_CACHE_OFFSET0, addr);
249 	WREG32(mmUVD_VCPU_CACHE_SIZE0, size);
253 	WREG32(mmUVD_VCPU_CACHE_OFFSET1, addr);
254 	WREG32(mmUVD_VCPU_CACHE_SIZE1, size);
259 	WREG32(mmUVD_VCPU_CACHE_OFFSET2, addr);
260 	WREG32(mmUVD_VCPU_CACHE_SIZE2, size);
264 	WREG32(mmUVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
268 	WREG32(mmUVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
270 	WREG32(mmUVD_UDEC_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
271 	WREG32(mmUVD_UDEC_DB_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
272 	WREG32(mmUVD_UDEC_DBW_ADDR_CONFIG, adev->gfx.config.gb_addr_config);
287 	WREG32(mmUVD_FW_START, keysel);
334 	WREG32(mmUVD_CGC_GATE, 0);
341 	WREG32(mmUVD_VCPU_CNTL,  1 << 9);
351 	WREG32(mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
352 	WREG32(mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
355 	WREG32(mmUVD_LMI_CTRL, 0x40 | (1 << 8) | (1 << 13) |
359 	WREG32(mmUVD_MPC_CNTL, tmp | 0x10);
361 	WREG32(mmUVD_MPC_SET_MUXA0, 0x40c2040);
362 	WREG32(mmUVD_MPC_SET_MUXA1, 0x0);
363 	WREG32(mmUVD_MPC_SET_MUXB0, 0x40c2040);
364 	WREG32(mmUVD_MPC_SET_MUXB1, 0x0);
365 	WREG32(mmUVD_MPC_SET_ALU, 0);
366 	WREG32(mmUVD_MPC_SET_MUX, 0x88);
414 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
417 	WREG32(mmUVD_RBC_RB_WPTR_CNTL, 0);
420 	WREG32(mmUVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
424 	WREG32(mmUVD_RBC_RB_RPTR, 0x0);
427 	WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
430 	WREG32(mmUVD_RBC_RB_BASE, ring->gpu_addr);
452 	WREG32(mmUVD_RBC_RB_CNTL, 0x11010101);
495 	WREG32(mmUVD_SOFT_RESET, UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
499 	WREG32(mmUVD_STATUS, 0);
608 			WREG32(mmUVD_CGC_CTRL, data);
617 			WREG32(mmUVD_CGC_CTRL, data);