Lines Matching refs:x
57 #define PACKET3_BASE_INDEX(x) ((x) << 0)
67 #define PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) & 0x7F) << 0)
68 #define PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) & 0xF) << 8)
69 #define PACKET3_ATOMIC_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
70 #define PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x)))
71 #define PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x)))
72 #define PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x)))
73 #define PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x)))
74 #define PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x)))
75 #define PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x)))
76 #define PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) & 0x1FFF) << 0)
107 #define WRITE_DATA_DST_SEL(x) ((x) << 8)
117 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
121 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
126 #define PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8)
127 #define PACKET3_WRITE_DATA__ADDR_INCR(x) ((((unsigned)(x)) & 0x1) << 16)
128 #define PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20)
129 #define PACKET3_WRITE_DATA__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
130 #define PACKET3_WRITE_DATA__DST_MMREG_ADDR(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
131 #define PACKET3_WRITE_DATA__DST_GDS_ADDR(x) ((((unsigned)(x)) & 0xFFFF) << 0)
132 #define PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
133 #define PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x))
134 #define PACKET3_WRITE_DATA__MODE(x) ((((unsigned)(x)) & 0x1) << 21)
135 #define PACKET3_WRITE_DATA__AID_ID(x) ((((unsigned)(x)) & 0x3) << 22)
136 #define PACKET3_WRITE_DATA__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 24)
137 #define PACKET3_WRITE_DATA__DST_MMREG_ADDR_LO(x) ((unsigned)(x))
138 #define PACKET3_WRITE_DATA__DST_MMREG_ADDR_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
167 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
176 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
180 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
184 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
188 #define PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) & 0x7) << 0)
189 #define PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) & 0x3) << 4)
190 #define PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) & 0x3) << 6)
191 #define PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 22)
192 #define PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) & 0x1) << 24)
193 #define PACKET3_WAIT_REG_MEM__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
194 #define PACKET3_WAIT_REG_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25)
195 #define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
196 #define PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((((unsigned)(x)) & 0X3FFFF) << 0)
197 #define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) & 0X3FFFF) << 0)
198 #define PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x))
199 #define PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
200 #define PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x))
201 #define PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x))
202 #define PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0)
203 #define PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31)
226 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
231 #define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21)
232 #define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30)
233 #define PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
234 #define PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x))
235 #define PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) & 0xFFFFF) << 0)
236 #define PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) & 0x1) << 20)
237 #define PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) & 0x1) << 21)
238 #define PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) & 0x1) << 23)
239 #define PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) & 0xF) << 24)
240 #define PACKET3_INDIRECT_BUFFER__CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 28)
241 #define PACKET3_INDIRECT_BUFFER__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 28)
242 #define PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31)
253 #define PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) & 0xF) << 0)
254 #define PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8)
255 #define PACKET3_COPY_DATA__SRC_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 13)
256 #define PACKET3_COPY_DATA__SRC_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 13)
257 #define PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) & 0x1) << 16)
258 #define PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20)
259 #define PACKET3_COPY_DATA__DST_CACHE_POLICY(x) ((((unsigned)(x)) & 0x3) << 25)
260 #define PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 29)
261 #define PACKET3_COPY_DATA__SRC_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
262 #define PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
263 #define PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
264 #define PACKET3_COPY_DATA__SRC_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0)
265 #define PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x))
266 #define PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x))
267 #define PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x))
268 #define PACKET3_COPY_DATA__DST_REG_OFFSET(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
269 #define PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
270 #define PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
271 #define PACKET3_COPY_DATA__DST_GDS_ADDR_LO(x) ((((unsigned)(x)) & 0xFFFF) << 0)
272 #define PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x))
273 #define PACKET3_COPY_DATA__MODE(x) ((((unsigned)(x)) & 0x1) << 21)
274 #define PACKET3_COPY_DATA__AID_ID(x) ((((unsigned)(x)) & 0x3) << 23)
275 #define PACKET3_COPY_DATA__DST_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25)
276 #define PACKET3_COPY_DATA__SRC_REG_OFFSET_LO(x) ((unsigned)(x))
277 #define PACKET3_COPY_DATA__SRC_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
278 #define PACKET3_COPY_DATA__DST_REG_OFFSET_LO(x) ((unsigned)(x))
279 #define PACKET3_COPY_DATA__DST_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
327 #define EVENT_TYPE(x) ((x) << 0)
328 #define EVENT_INDEX(x) ((x) << 8)
335 #define PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0)
336 #define PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8)
337 #define PACKET3_EVENT_WRITE__SAMP_PLST_CNTR_MODE(x) ((((unsigned)(x)) & 0x3) << 29)
338 #define PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) & 0x1) << 0)
339 #define PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
340 #define PACKET3_EVENT_WRITE__ADDRESS_HI(x) ((unsigned)(x))
355 #define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0)
356 #define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8)
367 #define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25)
375 #define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29)
382 #define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24)
387 #define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16)
407 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
411 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
415 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
420 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
424 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
458 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0)
465 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2)
472 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4)
473 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5)
474 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6)
475 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7)
476 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8)
477 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9)
478 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10)
479 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11)
486 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13)
487 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14)
488 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15)
489 #define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16)
496 #define PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x))
497 #define PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
498 #define PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x))
499 #define PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) & 0xFFFFFF) << 0)
500 #define PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0)
501 #define PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x7FFFF) << 0)
528 #define PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0)
529 #define PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) & 0x1F) << 23)
530 #define PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) & 0xF) << 28)
538 #define PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0)
559 # define FRAME_CMD(x) ((x) << 28)
561 * x=0: tmz_begin
562 * x=1: tmz_end
570 # define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0)
571 # define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4)
572 # define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5)
573 # define PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(x) ((x) << 29)
591 # define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0)
592 # define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16)
593 # define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29)
605 # define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
606 # define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8)
607 # define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13)
608 # define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16)
609 # define PACKET3_MAP_QUEUES_ME(x) ((x) << 18)
610 # define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21)
611 # define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24)
612 # define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
613 # define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
615 # define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1)
616 # define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2)
626 # define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0)
632 # define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4)
633 # define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26)
634 # define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29)
636 # define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0)
638 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2)
640 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2)
642 # define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0)
644 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2)
646 # define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2)
657 # define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0)
658 # define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28)
659 # define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30)
661 # define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0)
663 # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2)
664 # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25)
675 # define PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(x) ((x) << 0)