Lines Matching refs:GC
410 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, in mes_v11_0_reset_queue_mmio()
417 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); in mes_v11_0_reset_queue_mmio()
425 if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) in mes_v11_0_reset_queue_mmio()
441 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); in mes_v11_0_reset_queue_mmio()
442 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); in mes_v11_0_reset_queue_mmio()
446 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v11_0_reset_queue_mmio()
461 reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); in mes_v11_0_reset_queue_mmio()
465 reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); in mes_v11_0_reset_queue_mmio()
939 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); in mes_v11_0_get_fw_version()
942 RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); in mes_v11_0_get_fw_version()
956 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO, in mes_v11_0_enable()
958 WREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI, in mes_v11_0_enable()
961 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_HI), in mes_v11_0_enable()
962 RREG32_SOC15(GC, 0, regCP_MES_MSCRATCH_LO)); in mes_v11_0_enable()
965 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v11_0_enable()
969 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
980 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, in mes_v11_0_enable()
982 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, in mes_v11_0_enable()
992 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
999 data = RREG32_SOC15(GC, 0, regCP_MES_CNTL); in mes_v11_0_enable()
1008 WREG32_SOC15(GC, 0, regCP_MES_CNTL, data); in mes_v11_0_enable()
1039 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_CNTL, 0); in mes_v11_0_load_microcode()
1043 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START, in mes_v11_0_load_microcode()
1045 WREG32_SOC15(GC, 0, regCP_MES_PRGRM_CNTR_START_HI, in mes_v11_0_load_microcode()
1049 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_LO, in mes_v11_0_load_microcode()
1051 WREG32_SOC15(GC, 0, regCP_MES_IC_BASE_HI, in mes_v11_0_load_microcode()
1055 WREG32_SOC15(GC, 0, regCP_MES_MIBOUND_LO, 0x1FFFFF); in mes_v11_0_load_microcode()
1058 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_LO, in mes_v11_0_load_microcode()
1060 WREG32_SOC15(GC, 0, regCP_MES_MDBASE_HI, in mes_v11_0_load_microcode()
1064 WREG32_SOC15(GC, 0, regCP_MES_MDBOUND_LO, 0x7FFFF); in mes_v11_0_load_microcode()
1068 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); in mes_v11_0_load_microcode()
1071 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); in mes_v11_0_load_microcode()
1074 data = RREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL); in mes_v11_0_load_microcode()
1076 WREG32_SOC15(GC, 0, regCP_MES_IC_OP_CNTL, data); in mes_v11_0_load_microcode()
1224 data = RREG32_SOC15(GC, 0, regCP_HQD_VMID); in mes_v11_0_queue_init_register()
1226 WREG32_SOC15(GC, 0, regCP_HQD_VMID, data); in mes_v11_0_queue_init_register()
1229 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v11_0_queue_init_register()
1232 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v11_0_queue_init_register()
1235 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr_lo); in mes_v11_0_queue_init_register()
1236 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi); in mes_v11_0_queue_init_register()
1239 data = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL); in mes_v11_0_queue_init_register()
1241 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL, 0); in mes_v11_0_queue_init_register()
1244 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE, mqd->cp_hqd_pq_base_lo); in mes_v11_0_queue_init_register()
1245 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI, mqd->cp_hqd_pq_base_hi); in mes_v11_0_queue_init_register()
1248 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR, in mes_v11_0_queue_init_register()
1250 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI, in mes_v11_0_queue_init_register()
1254 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL, mqd->cp_hqd_pq_control); in mes_v11_0_queue_init_register()
1257 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR, in mes_v11_0_queue_init_register()
1259 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI, in mes_v11_0_queue_init_register()
1263 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in mes_v11_0_queue_init_register()
1267 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE, mqd->cp_hqd_persistent_state); in mes_v11_0_queue_init_register()
1270 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, mqd->cp_hqd_active); in mes_v11_0_queue_init_register()
1523 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) { in mes_v11_0_kiq_dequeue()
1524 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1); in mes_v11_0_kiq_dequeue()
1526 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) in mes_v11_0_kiq_dequeue()
1531 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v11_0_kiq_dequeue()
1536 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v11_0_kiq_dequeue()
1538 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); in mes_v11_0_kiq_dequeue()
1540 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO, 0); in mes_v11_0_kiq_dequeue()
1541 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI, 0); in mes_v11_0_kiq_dequeue()
1542 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR, 0); in mes_v11_0_kiq_dequeue()
1554 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v11_0_kiq_setting()
1557 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80); in mes_v11_0_kiq_setting()
1565 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS); in mes_v11_0_kiq_clear()
1567 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp); in mes_v11_0_kiq_clear()