amd/amdgpu/gmc_v7_0.c

102 		WREG32(mmBIF_FB_EN, 0);
106 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
119 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
123 	WREG32(mmBIF_FB_EN, tmp);
203 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
204 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
208 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(io_mc_regs++));
209 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(io_mc_regs++));
213 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(fw_data++));
216 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
217 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
218 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
270 		WREG32((0xb05 + j), 0x00000000);
271 		WREG32((0xb06 + j), 0x00000000);
272 		WREG32((0xb07 + j), 0x00000000);
273 		WREG32((0xb08 + j), 0x00000000);
274 		WREG32((0xb09 + j), 0x00000000);
276 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
285 		WREG32(mmVGA_HDP_CONTROL, tmp);
290 		WREG32(mmVGA_RENDER_CONTROL, tmp);
293 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
295 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
297 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
299 	WREG32(mmMC_VM_AGP_BASE, 0);
300 	WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
301 	WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
305 	WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
309 	WREG32(mmHDP_MISC_CNTL, tmp);
312 	WREG32(mmHDP_HOST_PATH_CNTL, tmp);
449 	WREG32(mmVM_INVALIDATE_REQUEST, mask);
474 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
538 	WREG32(mmVM_CONTEXT1_CNTL, tmp);
571 	WREG32(mmVM_PRT_CNTL, tmp);
579 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
580 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
581 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
582 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
583 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
584 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
585 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
586 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
588 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
589 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
590 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
591 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
592 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
593 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
594 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
595 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
630 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
640 	WREG32(mmVM_L2_CNTL, tmp);
643 	WREG32(mmVM_L2_CNTL2, tmp);
650 	WREG32(mmVM_L2_CNTL3, tmp);
652 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
653 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
654 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
655 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
657 	WREG32(mmVM_CONTEXT0_CNTL2, 0);
662 	WREG32(mmVM_CONTEXT0_CNTL, tmp);
664 	WREG32(0x575, 0);
665 	WREG32(0x576, 0);
666 	WREG32(0x577, 0);
673 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
674 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
677 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
680 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
685 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
687 	WREG32(mmVM_CONTEXT1_CNTL2, 4);
693 	WREG32(mmVM_CONTEXT1_CNTL, tmp);
702 		WREG32(mmCHUB_CONTROL, tmp);
741 	WREG32(mmVM_CONTEXT0_CNTL, 0);
742 	WREG32(mmVM_CONTEXT1_CNTL, 0);
748 	WREG32(mmMC_VM_MX_L1_TLB_CNTL, tmp);
752 	WREG32(mmVM_L2_CNTL, tmp);
753 	WREG32(mmVM_L2_CNTL2, 0);
837 			WREG32(mc_cg_registers[i], data);
854 			WREG32(mc_cg_registers[i], data);
894 		WREG32(mmHDP_HOST_PATH_CNTL, data);
910 		WREG32(mmHDP_MEM_POWER_LS, data);
1196 		WREG32(mmSRBM_SOFT_RESET, tmp);
1202 		WREG32(mmSRBM_SOFT_RESET, tmp);
1233 		WREG32(mmVM_CONTEXT0_CNTL, tmp);
1237 		WREG32(mmVM_CONTEXT1_CNTL, tmp);
1243 		WREG32(mmVM_CONTEXT0_CNTL, tmp);
1247 		WREG32(mmVM_CONTEXT1_CNTL, tmp);