amd/amdgpu/gmc_v6_0.c

78 		WREG32(mmBIF_FB_EN, 0);
82 		WREG32(mmMC_SHARED_BLACKOUT_CNTL, blackout | 1);
96 	WREG32(mmMC_SHARED_BLACKOUT_CNTL, tmp);
100 	WREG32(mmBIF_FB_EN, tmp);
173 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
174 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000010);
178 			WREG32(mmMC_SEQ_IO_DEBUG_INDEX, le32_to_cpup(new_io_mc_regs++));
179 			WREG32(mmMC_SEQ_IO_DEBUG_DATA, le32_to_cpup(new_io_mc_regs++));
183 			WREG32(mmMC_SEQ_SUP_PGM, le32_to_cpup(new_fw_data++));
186 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000008);
187 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000004);
188 		WREG32(mmMC_SEQ_SUP_CNTL, 0x00000001);
227 		WREG32((0xb05 + j), 0x00000000);
228 		WREG32((0xb06 + j), 0x00000000);
229 		WREG32((0xb07 + j), 0x00000000);
230 		WREG32((0xb08 + j), 0x00000000);
231 		WREG32((0xb09 + j), 0x00000000);
233 	WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0);
248 		WREG32(mmVGA_HDP_CONTROL, tmp);
253 		WREG32(mmVGA_RENDER_CONTROL, tmp);
256 	WREG32(mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
258 	WREG32(mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
260 	WREG32(mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
262 	WREG32(mmMC_VM_AGP_BASE, 0);
263 	WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22);
264 	WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22);
357 	WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
410 	WREG32(mmVM_CONTEXT1_CNTL, tmp);
441 	WREG32(mmVM_PRT_CNTL, tmp);
449 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, low);
450 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, low);
451 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, low);
452 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, low);
453 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, high);
454 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, high);
455 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, high);
456 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, high);
458 		WREG32(mmVM_PRT_APERTURE0_LOW_ADDR, 0xfffffff);
459 		WREG32(mmVM_PRT_APERTURE1_LOW_ADDR, 0xfffffff);
460 		WREG32(mmVM_PRT_APERTURE2_LOW_ADDR, 0xfffffff);
461 		WREG32(mmVM_PRT_APERTURE3_LOW_ADDR, 0xfffffff);
462 		WREG32(mmVM_PRT_APERTURE0_HIGH_ADDR, 0x0);
463 		WREG32(mmVM_PRT_APERTURE1_HIGH_ADDR, 0x0);
464 		WREG32(mmVM_PRT_APERTURE2_HIGH_ADDR, 0x0);
465 		WREG32(mmVM_PRT_APERTURE3_HIGH_ADDR, 0x0);
484 	WREG32(mmMC_VM_MX_L1_TLB_CNTL,
492 	WREG32(mmVM_L2_CNTL,
499 	WREG32(mmVM_L2_CNTL2,
504 	WREG32(mmVM_L2_CNTL3,
509 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
510 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
511 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
512 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
514 	WREG32(mmVM_CONTEXT0_CNTL2, 0);
515 	WREG32(mmVM_CONTEXT0_CNTL,
520 	WREG32(0x575, 0);
521 	WREG32(0x576, 0);
522 	WREG32(0x577, 0);
526 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
527 	WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
534 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
537 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
542 	WREG32(mmVM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
544 	WREG32(mmVM_CONTEXT1_CNTL2, 4);
545 	WREG32(mmVM_CONTEXT1_CNTL,
592 	WREG32(mmVM_CONTEXT0_CNTL, 0);
593 	WREG32(mmVM_CONTEXT1_CNTL, 0);
595 	WREG32(mmMC_VM_MX_L1_TLB_CNTL,
599 	WREG32(mmVM_L2_CNTL,
604 	WREG32(mmVM_L2_CNTL2, 0);
605 	WREG32(mmVM_L2_CNTL3,
679 			WREG32(mc_cg_registers[i], data);
696 			WREG32(mc_cg_registers[i], data);
736 		WREG32(mmHDP_HOST_PATH_CNTL, data);
752 		WREG32(mmHDP_MEM_POWER_LS, data);
1012 		WREG32(mmSRBM_SOFT_RESET, tmp);
1018 		WREG32(mmSRBM_SOFT_RESET, tmp);
1047 		WREG32(mmVM_CONTEXT0_CNTL, tmp);
1050 		WREG32(mmVM_CONTEXT1_CNTL, tmp);
1055 		WREG32(mmVM_CONTEXT0_CNTL, tmp);
1058 		WREG32(mmVM_CONTEXT1_CNTL, tmp);