422 	uint32_t se, cu, simd, wave;  in gfx_v9_4_2_log_wave_assignment()  local
437 			for (simd = 0; simd < SIMD_ID_MAX; simd++) {  in gfx_v9_4_2_log_wave_assignment()
456 	uint32_t se, cu, simd, wave;  in gfx_v9_4_2_wait_for_waves_assigned()  local
467 				for (simd = 0; simd < SIMD_ID_MAX; simd++)  in gfx_v9_4_2_wait_for_waves_assigned()
1816 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t ad…  in wave_read_ind()  argument
1820 		(simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |  in wave_read_ind()
1830 	uint32_t i, simd, wave;  in gfx_v9_4_2_log_cu_timeout_status()  local
1841 		simd = i / cu_info->max_waves_per_simd;  in gfx_v9_4_2_log_cu_timeout_status()
1844 		wave_status = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);  in gfx_v9_4_2_log_cu_timeout_status()
1845 		wave_pc_lo = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);  in gfx_v9_4_2_log_cu_timeout_status()
1846 		wave_pc_hi = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);  in gfx_v9_4_2_log_cu_timeout_status()
1848 			wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);  in gfx_v9_4_2_log_cu_timeout_status()
1850 			wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);  in gfx_v9_4_2_log_cu_timeout_status()
1852 			wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);  in gfx_v9_4_2_log_cu_timeout_status()
1854 			wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);  in gfx_v9_4_2_log_cu_timeout_status()
1855 		wave_ib_sts = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);  in gfx_v9_4_2_log_cu_timeout_status()
1860 			simd, wave, wave_status,  in gfx_v9_4_2_log_cu_timeout_status()