Lines Matching refs:GC
86 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS),
87 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2),
88 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3),
89 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1),
90 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2),
91 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3),
92 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1),
93 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1),
94 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT),
95 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT),
96 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT),
97 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2),
98 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2),
99 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS),
100 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR),
101 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0),
102 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE),
103 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
104 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR),
105 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE),
106 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR),
107 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR),
108 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
109 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ),
110 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
111 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
112 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
113 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO),
114 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI),
115 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ),
116 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS),
117 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS),
118 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS),
119 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS),
120 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2),
121 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS),
122 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS),
123 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES),
124 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS),
125 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS),
126 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL),
127 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32),
128 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32),
129 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL),
131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL),
132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR),
133 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR),
134 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR),
135 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS),
136 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0),
137 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1),
138 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR),
140 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
141 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
142 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
143 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
144 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
145 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
146 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
147 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP),
149 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0),
150 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1),
151 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE2),
152 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3)
157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID),
158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE),
159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY),
160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY),
161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM),
162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE),
163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI),
164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR),
165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),
166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),
167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL),
168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL),
169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR),
170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI),
171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR),
172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL),
173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST),
174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR),
175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI),
176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL),
177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR),
178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR),
179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS),
180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO),
181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI),
182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL),
183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET),
184 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE),
185 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET),
186 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE),
187 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE),
188 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR),
189 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM),
190 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO),
191 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI),
192 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET),
193 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT),
194 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET),
195 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS),
197 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
198 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
199 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
200 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
201 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
202 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
203 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
204 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP),
209 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_ACTIVE),
210 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_VMID),
211 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY),
212 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUANTUM),
213 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE),
214 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_BASE_HI),
215 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_OFFSET),
216 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CNTL),
217 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_CSMD_RPTR),
218 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR),
219 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_WPTR_HI),
220 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST),
221 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_MAPPED),
222 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_QUE_MGR_CONTROL),
223 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_CONTROL0),
224 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HQD_HQ_STATUS0),
225 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR),
226 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_MQD_BASE_ADDR_HI),
227 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO),
228 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI),
229 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR),
230 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO),
231 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI),
232 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ),
233 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ),
235 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
236 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
237 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
238 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
239 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
240 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
241 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
242 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP),
243 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
244 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
245 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
246 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
247 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
248 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
249 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
250 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP),
254 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f),
255 SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000),
256 SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020)
260 SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000),
454 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
736 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
737 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
738 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
739 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
740 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
741 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
742 reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
818 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
821 return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
828 WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
834 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
1326 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1327 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1329 WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1345 data = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1348 WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, data);
1349 WREG32_SOC15(GC, 0, regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK);
1691 WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1698 gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_CC_GC_SA_UNIT_DISABLE);
1702 gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGRBM_GC_USER_SA_UNIT_DISABLE);
1717 gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1721 gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1785 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1786 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1789 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1791 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);
1812 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1825 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1831 WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1849 return SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
1868 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
1870 return SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
1890 tmp = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
1899 WREG32_SOC15_IP(GC, cp_int_cntl_reg, tmp);
1909 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1911 WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1913 WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1920 u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1923 WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1928 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1930 WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1939 rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1953 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1963 WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1972 tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1975 WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1989 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1993 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1996 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2012 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
2017 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
2021 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2027 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
2031 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
2035 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
2037 tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
2040 WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
2089 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
2092 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
2126 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2129 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2135 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2138 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2143 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2148 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2151 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2157 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2160 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2165 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2170 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2173 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2179 tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2184 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2191 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2204 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2207 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2214 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2221 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2230 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2246 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2249 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2256 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2263 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2272 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2288 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2291 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2305 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2306 bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2335 u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2339 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2342 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2410 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2412 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2415 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2419 WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2427 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2440 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2442 WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2445 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2461 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2463 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2469 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2472 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2475 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2477 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2480 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2554 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2556 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2559 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2563 WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2571 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2584 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2586 WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2590 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2606 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2608 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2614 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2617 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2620 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2622 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2625 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2669 WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
2671 WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
2684 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
2687 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
2695 tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
2705 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
2709 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
2711 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2723 WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
2726 WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
2737 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2741 WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
2742 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2746 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2747 WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
2751 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
2753 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
2757 WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
2760 WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
2761 WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2763 WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
2782 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2803 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
2869 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2873 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2875 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2878 WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2884 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO,
2887 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2891 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2893 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2900 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2902 WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2906 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2919 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2921 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2925 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2948 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
2951 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp | 0x80);
2957 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
2959 WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
2963 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
2965 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3290 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3293 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3296 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3298 WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3302 WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3306 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3310 if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3311 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3313 if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3317 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3319 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3321 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3323 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3328 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3330 WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3334 WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3338 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3340 WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3344 WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3348 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3350 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3354 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3356 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3361 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3363 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3367 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3371 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3373 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3377 WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
3379 WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
3383 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
3387 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3579 gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
3615 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
3617 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
3619 data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
3621 WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
3806 tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3808 WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3836 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
3851 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
3947 rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
3960 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
3964 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
3974 WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
3985 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
3993 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4003 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
4013 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
4015 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data);
4021 uint32_t reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL);
4086 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4099 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4102 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4117 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4120 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4135 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4138 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4145 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4147 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4152 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4154 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4156 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4160 data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4162 WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4166 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4175 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4178 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4186 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4201 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4208 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4212 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4219 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4232 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4242 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4253 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4261 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4319 data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4336 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4345 data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4369 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
4370 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
4386 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
4388 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
4571 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
4731 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
4744 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4749 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4752 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4757 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4779 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
4782 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
4795 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4800 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4803 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
4808 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
4914 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4918 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4928 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4932 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4960 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4964 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
4974 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
4978 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5005 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5009 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5305 WREG32_SOC15(GC, 0, regCP_ME_CNTL, reset_pipe);
5306 WREG32_SOC15(GC, 0, regCP_ME_CNTL, clean_pipe);
5308 r = (RREG32(SOC15_REG_OFFSET(GC, 0, regCP_GFX_RS64_INSTR_PNTR1)) << 2) -
5371 reset_pipe = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
5403 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, reset_pipe);
5404 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, clean_pipe);
5405 r = (RREG32_SOC15(GC, 0, regCP_MEC_RS64_INSTR_PNTR) << 2) -
5424 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, reset_pipe);
5425 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, clean_pipe);
5709 WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
5715 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
5716 data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);