Lines Matching refs:fb_format

1797 	uint32_t fb_format, fb_pitch_pixels;  in dce_v8_0_crtc_do_set_base()  local
1836 fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v8_0_crtc_do_set_base()
1841 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v8_0_crtc_do_set_base()
1849 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v8_0_crtc_do_set_base()
1857 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v8_0_crtc_do_set_base()
1864 fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v8_0_crtc_do_set_base()
1872 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v8_0_crtc_do_set_base()
1880 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v8_0_crtc_do_set_base()
1890 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v8_0_crtc_do_set_base()
1900 fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | in dce_v8_0_crtc_do_set_base()
1923 fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT); in dce_v8_0_crtc_do_set_base()
1924 fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); in dce_v8_0_crtc_do_set_base()
1925 fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT); in dce_v8_0_crtc_do_set_base()
1926 fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT); in dce_v8_0_crtc_do_set_base()
1927 fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT); in dce_v8_0_crtc_do_set_base()
1928 fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT); in dce_v8_0_crtc_do_set_base()
1929 fb_format |= (DISPLAY_MICRO_TILING << GRPH_CONTROL__GRPH_MICRO_TILE_MODE__SHIFT); in dce_v8_0_crtc_do_set_base()
1931 fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT); in dce_v8_0_crtc_do_set_base()
1934 fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT); in dce_v8_0_crtc_do_set_base()
1951 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v8_0_crtc_do_set_base()
2602 uint32_t fb_format; in dce_v8_0_panic_flush() local
2612 fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset); in dce_v8_0_panic_flush()
2613 fb_format &= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK; in dce_v8_0_panic_flush()
2614 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format); in dce_v8_0_panic_flush()