1888 	uint32_t fb_format, fb_pitch_pixels, pipe_config;  in dce_v6_0_crtc_do_set_base()  local
1924 		fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v6_0_crtc_do_set_base()
1929 		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v6_0_crtc_do_set_base()
1937 		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v6_0_crtc_do_set_base()
1945 		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v6_0_crtc_do_set_base()
1952 		fb_format = ((GRPH_DEPTH_16BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v6_0_crtc_do_set_base()
1960 		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v6_0_crtc_do_set_base()
1968 		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v6_0_crtc_do_set_base()
1978 		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v6_0_crtc_do_set_base()
1988 		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |  in dce_v6_0_crtc_do_set_base()
2011 		fb_format |= (num_banks << GRPH_CONTROL__GRPH_NUM_BANKS__SHIFT);  in dce_v6_0_crtc_do_set_base()
2012 		fb_format |= (GRPH_ARRAY_2D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);  in dce_v6_0_crtc_do_set_base()
2013 		fb_format |= (tile_split << GRPH_CONTROL__GRPH_TILE_SPLIT__SHIFT);  in dce_v6_0_crtc_do_set_base()
2014 		fb_format |= (bankw << GRPH_CONTROL__GRPH_BANK_WIDTH__SHIFT);  in dce_v6_0_crtc_do_set_base()
2015 		fb_format |= (bankh << GRPH_CONTROL__GRPH_BANK_HEIGHT__SHIFT);  in dce_v6_0_crtc_do_set_base()
2016 		fb_format |= (mtaspect << GRPH_CONTROL__GRPH_MACRO_TILE_ASPECT__SHIFT);  in dce_v6_0_crtc_do_set_base()
2018 		fb_format |= (GRPH_ARRAY_1D_TILED_THIN1 << GRPH_CONTROL__GRPH_ARRAY_MODE__SHIFT);  in dce_v6_0_crtc_do_set_base()
2022 	fb_format |= (pipe_config << GRPH_CONTROL__GRPH_PIPE_CONFIG__SHIFT);  in dce_v6_0_crtc_do_set_base()
2039 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v6_0_crtc_do_set_base()
2643 	uint32_t fb_format;  in dce_v6_0_panic_flush()  local
2653 	fb_format = RREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset);  in dce_v6_0_panic_flush()
2654 	fb_format &= ~GRPH_CONTROL__GRPH_ARRAY_MODE_MASK;  in dce_v6_0_panic_flush()
2655 	WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);  in dce_v6_0_panic_flush()