Lines Matching full:ring
96 /* Direct submission to the ring buffer during init and reset. */
121 /* sync_seq is protected by ring emission lock */
138 * are no longer in use by the associated ring on the GPU and
146 struct amdgpu_ring *ring; member
162 void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error);
163 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring);
167 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring);
168 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
175 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct amdgpu_fence *af,
177 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
179 bool amdgpu_fence_process(struct amdgpu_ring *ring);
180 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring);
181 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
184 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring);
188 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring);
189 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq,
196 /* provided by hw blocks that expose a ring buffer for commands */
202 * use ring buffers. The type field just identifies which component the
203 * ring buffer is associated with.
214 * that initializes the ring.
224 * Optional extra space in bytes that is added to the ring size
225 * when allocating the BO that holds the contents of the ring.
226 * This space isn't used for command submission to the ring,
229 * specific ring to initialize this space.
233 /* ring read/write ptr handling */
234 u64 (*get_rptr)(struct amdgpu_ring *ring);
235 u64 (*get_wptr)(struct amdgpu_ring *ring);
236 void (*set_wptr)(struct amdgpu_ring *ring);
248 void (*emit_ib)(struct amdgpu_ring *ring,
252 void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
254 void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
255 void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
257 void (*emit_hdp_flush)(struct amdgpu_ring *ring);
258 void (*emit_gds_switch)(struct amdgpu_ring *ring, uint32_t vmid,
263 int (*test_ring)(struct amdgpu_ring *ring);
264 int (*test_ib)(struct amdgpu_ring *ring, long timeout);
266 void (*insert_nop)(struct amdgpu_ring *ring, uint32_t count);
267 void (*insert_start)(struct amdgpu_ring *ring);
268 void (*insert_end)(struct amdgpu_ring *ring);
270 void (*pad_ib)(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
271 unsigned (*init_cond_exec)(struct amdgpu_ring *ring, uint64_t addr);
273 void (*begin_use)(struct amdgpu_ring *ring);
274 void (*end_use)(struct amdgpu_ring *ring);
275 void (*emit_switch_buffer) (struct amdgpu_ring *ring);
276 void (*emit_cntxcntl) (struct amdgpu_ring *ring, uint32_t flags);
277 void (*emit_gfx_shadow)(struct amdgpu_ring *ring, u64 shadow_va, u64 csa_va,
279 void (*emit_rreg)(struct amdgpu_ring *ring, uint32_t reg,
281 void (*emit_wreg)(struct amdgpu_ring *ring, uint32_t reg, uint32_t val);
282 void (*emit_reg_wait)(struct amdgpu_ring *ring, uint32_t reg,
284 void (*emit_reg_write_reg_wait)(struct amdgpu_ring *ring,
287 void (*emit_frame_cntl)(struct amdgpu_ring *ring, bool start,
289 /* Try to soft recover the ring to make the fence signal */
290 void (*soft_recovery)(struct amdgpu_ring *ring, unsigned vmid);
291 int (*preempt_ib)(struct amdgpu_ring *ring);
292 void (*emit_mem_sync)(struct amdgpu_ring *ring);
293 void (*emit_wave_limit)(struct amdgpu_ring *ring, bool enable);
294 void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset);
295 void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset);
296 void (*patch_de)(struct amdgpu_ring *ring, unsigned offset);
297 int (*reset)(struct amdgpu_ring *ring, unsigned int vmid,
299 void (*emit_cleaner_shader)(struct amdgpu_ring *ring);
303 * amdgpu_ring - Holds ring information
312 uint32_t *ring; member
323 * This is part of the Ring buffer implementation and represents the
340 * Maximum number of DWords for ring allocation. This information is
341 * provided at the ring initialization time, and each IP block can
351 * ring. This value is updated based on the ring manipulation.
371 * thresholding. Buffer mask initialized during the ring buffer
460 int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw);
461 void amdgpu_ring_ib_begin(struct amdgpu_ring *ring);
462 void amdgpu_ring_ib_end(struct amdgpu_ring *ring);
463 void amdgpu_ring_ib_on_emit_cntl(struct amdgpu_ring *ring);
464 void amdgpu_ring_ib_on_emit_ce(struct amdgpu_ring *ring);
465 void amdgpu_ring_ib_on_emit_de(struct amdgpu_ring *ring);
467 void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count);
468 void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib);
469 void amdgpu_ring_commit(struct amdgpu_ring *ring);
470 void amdgpu_ring_undo(struct amdgpu_ring *ring);
471 int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
475 void amdgpu_ring_fini(struct amdgpu_ring *ring);
476 void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
479 bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
482 static inline void amdgpu_ring_set_preempt_cond_exec(struct amdgpu_ring *ring, in amdgpu_ring_set_preempt_cond_exec() argument
485 *ring->cond_exe_cpu_addr = cond_exec; in amdgpu_ring_set_preempt_cond_exec()
488 static inline void amdgpu_ring_clear_ring(struct amdgpu_ring *ring) in amdgpu_ring_clear_ring() argument
490 memset32(ring->ring, ring->funcs->nop, ring->buf_mask + 1); in amdgpu_ring_clear_ring()
493 static inline void amdgpu_ring_write(struct amdgpu_ring *ring, uint32_t v) in amdgpu_ring_write() argument
495 ring->ring[ring->wptr++ & ring->buf_mask] = v; in amdgpu_ring_write()
496 ring->wptr &= ring->ptr_mask; in amdgpu_ring_write()
497 ring->count_dw--; in amdgpu_ring_write()
500 static inline void amdgpu_ring_write_multiple(struct amdgpu_ring *ring, in amdgpu_ring_write_multiple() argument
505 occupied = ring->wptr & ring->buf_mask; in amdgpu_ring_write_multiple()
506 chunk1 = ring->buf_mask + 1 - occupied; in amdgpu_ring_write_multiple()
513 memcpy(&ring->ring[occupied], src, chunk1); in amdgpu_ring_write_multiple()
517 memcpy(ring->ring, src, chunk2); in amdgpu_ring_write_multiple()
520 ring->wptr += count_dw; in amdgpu_ring_write_multiple()
521 ring->wptr &= ring->ptr_mask; in amdgpu_ring_write_multiple()
522 ring->count_dw -= count_dw; in amdgpu_ring_write_multiple()
527 * @ring: amdgpu_ring structure
532 static inline void amdgpu_ring_patch_cond_exec(struct amdgpu_ring *ring, in amdgpu_ring_patch_cond_exec() argument
537 if (!ring->funcs->init_cond_exec) in amdgpu_ring_patch_cond_exec()
540 WARN_ON(offset > ring->buf_mask); in amdgpu_ring_patch_cond_exec()
541 WARN_ON(ring->ring[offset] != 0); in amdgpu_ring_patch_cond_exec()
543 cur = (ring->wptr - 1) & ring->buf_mask; in amdgpu_ring_patch_cond_exec()
545 cur += ring->ring_size >> 2; in amdgpu_ring_patch_cond_exec()
546 ring->ring[offset] = cur - offset; in amdgpu_ring_patch_cond_exec()
549 int amdgpu_ring_test_helper(struct amdgpu_ring *ring);
552 struct amdgpu_ring *ring);
554 int amdgpu_ring_init_mqd(struct amdgpu_ring *ring);
572 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
578 bool amdgpu_ring_sched_ready(struct amdgpu_ring *ring);
579 void amdgpu_ring_backup_unprocessed_commands(struct amdgpu_ring *ring,
581 void amdgpu_ring_reset_helper_begin(struct amdgpu_ring *ring,
583 int amdgpu_ring_reset_helper_end(struct amdgpu_ring *ring,
585 bool amdgpu_ring_is_reset_type_supported(struct amdgpu_ring *ring,