Lines Matching full:control
131 * add to control->i2c_address, and then tell I2C layer to read
176 struct amdgpu_ras_eeprom_control *control) in __get_eeprom_i2c_addr() argument
181 if (!control) in __get_eeprom_i2c_addr()
194 control->i2c_address = ((u32) i2c_addr) << 16; in __get_eeprom_i2c_addr()
203 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
207 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
209 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
212 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
217 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
219 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
224 control->i2c_address = EEPROM_I2C_MADDR_0; in __get_eeprom_i2c_addr()
226 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
232 control->i2c_address = EEPROM_I2C_MADDR_4; in __get_eeprom_i2c_addr()
265 static int __write_table_header(struct amdgpu_ras_eeprom_control *control) in __write_table_header() argument
268 struct amdgpu_device *adev = to_amdgpu_device(control); in __write_table_header()
272 __encode_table_header_to_buf(&control->tbl_hdr, buf); in __write_table_header()
277 control->i2c_address + in __write_table_header()
278 control->ras_header_offset, in __write_table_header()
322 static int __write_table_ras_info(struct amdgpu_ras_eeprom_control *control) in __write_table_ras_info() argument
324 struct amdgpu_device *adev = to_amdgpu_device(control); in __write_table_ras_info()
335 __encode_table_ras_info_to_buf(&control->tbl_rai, buf); in __write_table_ras_info()
340 control->i2c_address + in __write_table_ras_info()
341 control->ras_info_offset, in __write_table_ras_info()
361 static u8 __calc_hdr_byte_sum(const struct amdgpu_ras_eeprom_control *control) in __calc_hdr_byte_sum() argument
368 sz = sizeof(control->tbl_hdr) - sizeof(control->tbl_hdr.checksum); in __calc_hdr_byte_sum()
369 pp = (u8 *) &control->tbl_hdr; in __calc_hdr_byte_sum()
377 static u8 __calc_ras_info_byte_sum(const struct amdgpu_ras_eeprom_control *control) in __calc_ras_info_byte_sum() argument
383 sz = sizeof(control->tbl_rai); in __calc_ras_info_byte_sum()
384 pp = (u8 *) &control->tbl_rai; in __calc_ras_info_byte_sum()
393 struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_correct_header_tag() argument
396 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_correct_header_tag()
408 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_correct_header_tag()
411 res = __write_table_header(control); in amdgpu_ras_eeprom_correct_header_tag()
412 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_correct_header_tag()
417 static void amdgpu_ras_set_eeprom_table_version(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_set_eeprom_table_version() argument
419 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_set_eeprom_table_version()
420 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_set_eeprom_table_version()
438 * @control: pointer to control structure
443 int amdgpu_ras_eeprom_reset_table(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_reset_table() argument
445 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_reset_table()
446 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_reset_table()
447 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; in amdgpu_ras_eeprom_reset_table()
453 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_reset_table()
457 amdgpu_ras_set_eeprom_table_version(control); in amdgpu_ras_eeprom_reset_table()
465 control->ras_record_offset = RAS_RECORD_START_V2_1; in amdgpu_ras_eeprom_reset_table()
466 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; in amdgpu_ras_eeprom_reset_table()
478 control->ras_record_offset = RAS_RECORD_START; in amdgpu_ras_eeprom_reset_table()
479 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; in amdgpu_ras_eeprom_reset_table()
482 csum = __calc_hdr_byte_sum(control); in amdgpu_ras_eeprom_reset_table()
484 csum += __calc_ras_info_byte_sum(control); in amdgpu_ras_eeprom_reset_table()
487 res = __write_table_header(control); in amdgpu_ras_eeprom_reset_table()
489 res = __write_table_ras_info(control); in amdgpu_ras_eeprom_reset_table()
500 control->ras_num_recs = 0; in amdgpu_ras_eeprom_reset_table()
501 control->ras_num_bad_pages = 0; in amdgpu_ras_eeprom_reset_table()
502 control->ras_num_mca_recs = 0; in amdgpu_ras_eeprom_reset_table()
503 control->ras_num_pa_recs = 0; in amdgpu_ras_eeprom_reset_table()
504 control->ras_fri = 0; in amdgpu_ras_eeprom_reset_table()
506 amdgpu_dpm_send_hbm_bad_pages_num(adev, control->ras_num_bad_pages); in amdgpu_ras_eeprom_reset_table()
508 control->bad_channel_bitmap = 0; in amdgpu_ras_eeprom_reset_table()
509 amdgpu_dpm_send_hbm_bad_channel_flag(adev, control->bad_channel_bitmap); in amdgpu_ras_eeprom_reset_table()
512 amdgpu_ras_debugfs_set_ret_size(control); in amdgpu_ras_eeprom_reset_table()
514 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_reset_table()
520 __encode_table_record_to_buf(struct amdgpu_ras_eeprom_control *control, in __encode_table_record_to_buf() argument
548 __decode_table_record_from_buf(struct amdgpu_ras_eeprom_control *control, in __decode_table_record_from_buf() argument
614 * @control: pointer to control structure
619 * The caller must hold the table mutex in @control.
622 static int __amdgpu_ras_eeprom_write(struct amdgpu_ras_eeprom_control *control, in __amdgpu_ras_eeprom_write() argument
625 struct amdgpu_device *adev = to_amdgpu_device(control); in __amdgpu_ras_eeprom_write()
633 control->i2c_address + in __amdgpu_ras_eeprom_write()
634 RAS_INDEX_TO_OFFSET(control, fri), in __amdgpu_ras_eeprom_write()
654 amdgpu_ras_eeprom_append_table(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_append_table() argument
658 struct amdgpu_ras *con = amdgpu_ras_get_context(to_amdgpu_device(control)); in amdgpu_ras_eeprom_append_table()
659 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_append_table()
672 __encode_table_record_to_buf(control, &record[i], pp); in amdgpu_ras_eeprom_append_table()
675 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && in amdgpu_ras_eeprom_append_table()
676 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { in amdgpu_ras_eeprom_append_table()
677 control->bad_channel_bitmap |= 1 << record[i].mem_channel; in amdgpu_ras_eeprom_append_table()
686 * Let N = control->ras_max_num_record_count, then we have, in amdgpu_ras_eeprom_append_table()
709 a = control->ras_fri + control->ras_num_recs; in amdgpu_ras_eeprom_append_table()
711 if (b < control->ras_max_record_count) { in amdgpu_ras_eeprom_append_table()
712 res = __amdgpu_ras_eeprom_write(control, buf, a, num); in amdgpu_ras_eeprom_append_table()
713 } else if (a < control->ras_max_record_count) { in amdgpu_ras_eeprom_append_table()
716 g0 = control->ras_max_record_count - a; in amdgpu_ras_eeprom_append_table()
717 g1 = b % control->ras_max_record_count + 1; in amdgpu_ras_eeprom_append_table()
718 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); in amdgpu_ras_eeprom_append_table()
721 res = __amdgpu_ras_eeprom_write(control, in amdgpu_ras_eeprom_append_table()
726 if (g1 > control->ras_fri) in amdgpu_ras_eeprom_append_table()
727 control->ras_fri = g1 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
729 a %= control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
730 b %= control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
734 res = __amdgpu_ras_eeprom_write(control, buf, a, num); in amdgpu_ras_eeprom_append_table()
737 if (b >= control->ras_fri) in amdgpu_ras_eeprom_append_table()
738 control->ras_fri = (b + 1) % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
746 g0 = control->ras_max_record_count - a; in amdgpu_ras_eeprom_append_table()
748 res = __amdgpu_ras_eeprom_write(control, buf, a, g0); in amdgpu_ras_eeprom_append_table()
751 res = __amdgpu_ras_eeprom_write(control, in amdgpu_ras_eeprom_append_table()
756 control->ras_fri = g1 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
759 control->ras_num_recs = 1 + (control->ras_max_record_count + b in amdgpu_ras_eeprom_append_table()
760 - control->ras_fri) in amdgpu_ras_eeprom_append_table()
761 % control->ras_max_record_count; in amdgpu_ras_eeprom_append_table()
765 control->ras_num_pa_recs += num; in amdgpu_ras_eeprom_append_table()
767 control->ras_num_mca_recs += num; in amdgpu_ras_eeprom_append_table()
769 control->ras_num_bad_pages = con->bad_page_num; in amdgpu_ras_eeprom_append_table()
776 amdgpu_ras_eeprom_update_header(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_update_header() argument
778 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_update_header()
787 control->ras_num_bad_pages > ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
790 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
798 control->tbl_hdr.header = RAS_TABLE_HDR_BAD; in amdgpu_ras_eeprom_update_header()
799 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) { in amdgpu_ras_eeprom_update_header()
800 control->tbl_rai.rma_status = GPU_RETIRED__ECC_REACH_THRESHOLD; in amdgpu_ras_eeprom_update_header()
801 control->tbl_rai.health_percent = 0; in amdgpu_ras_eeprom_update_header()
810 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()
811 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + in amdgpu_ras_eeprom_update_header()
813 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
815 control->tbl_hdr.tbl_size = RAS_TABLE_HEADER_SIZE + in amdgpu_ras_eeprom_update_header()
816 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
817 control->tbl_hdr.checksum = 0; in amdgpu_ras_eeprom_update_header()
819 buf_size = control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in amdgpu_ras_eeprom_update_header()
820 buf = kcalloc(control->ras_num_recs, RAS_TABLE_RECORD_SIZE, GFP_KERNEL); in amdgpu_ras_eeprom_update_header()
824 control->tbl_hdr.tbl_size); in amdgpu_ras_eeprom_update_header()
831 control->i2c_address + in amdgpu_ras_eeprom_update_header()
832 control->ras_record_offset, in amdgpu_ras_eeprom_update_header()
850 control->tbl_hdr.version >= RAS_TABLE_VER_V2_1 && in amdgpu_ras_eeprom_update_header()
851 control->ras_num_bad_pages <= ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_update_header()
852 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - in amdgpu_ras_eeprom_update_header()
853 control->ras_num_bad_pages) * 100) / in amdgpu_ras_eeprom_update_header()
862 csum += __calc_hdr_byte_sum(control); in amdgpu_ras_eeprom_update_header()
863 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_update_header()
864 csum += __calc_ras_info_byte_sum(control); in amdgpu_ras_eeprom_update_header()
867 control->tbl_hdr.checksum = csum; in amdgpu_ras_eeprom_update_header()
868 res = __write_table_header(control); in amdgpu_ras_eeprom_update_header()
869 if (!res && control->tbl_hdr.version > RAS_TABLE_VER_V1) in amdgpu_ras_eeprom_update_header()
870 res = __write_table_ras_info(control); in amdgpu_ras_eeprom_update_header()
876 int amdgpu_ras_eeprom_update_record_num(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_update_record_num() argument
878 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_update_record_num()
884 control->ras_num_recs_old = control->ras_num_recs; in amdgpu_ras_eeprom_update_record_num()
891 &(control->ras_num_recs), RAS_SMU_MESSAGE_TIMEOUT_MS); in amdgpu_ras_eeprom_update_record_num()
893 (control->ras_num_recs_old == control->ras_num_recs)) { in amdgpu_ras_eeprom_update_record_num()
908 if (!ret && (control->ras_num_recs_old == control->ras_num_recs)) in amdgpu_ras_eeprom_update_record_num()
914 static int amdgpu_ras_smu_eeprom_append(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_smu_eeprom_append() argument
916 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_smu_eeprom_append()
922 control->ras_num_bad_pages = con->bad_page_num; in amdgpu_ras_smu_eeprom_append()
925 control->ras_num_bad_pages > con->bad_page_cnt_threshold) { in amdgpu_ras_smu_eeprom_append()
928 control->ras_num_bad_pages, con->bad_page_cnt_threshold); in amdgpu_ras_smu_eeprom_append()
943 * @control: pointer to control structure
949 * can be appended is between 1 and control->ras_max_record_count,
954 int amdgpu_ras_eeprom_append(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_append() argument
958 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_append()
966 return amdgpu_ras_smu_eeprom_append(control); in amdgpu_ras_eeprom_append()
971 } else if (num > control->ras_max_record_count) { in amdgpu_ras_eeprom_append()
974 num, control->ras_max_record_count); in amdgpu_ras_eeprom_append()
985 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_append()
987 res = amdgpu_ras_eeprom_append_table(control, record, num); in amdgpu_ras_eeprom_append()
989 res = amdgpu_ras_eeprom_update_header(control); in amdgpu_ras_eeprom_append()
991 amdgpu_ras_debugfs_set_ret_size(control); in amdgpu_ras_eeprom_append()
993 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_append()
1004 * @control: pointer to control structure
1009 * The caller must hold the table mutex in @control.
1012 static int __amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, in __amdgpu_ras_eeprom_read() argument
1015 struct amdgpu_device *adev = to_amdgpu_device(control); in __amdgpu_ras_eeprom_read()
1023 control->i2c_address + in __amdgpu_ras_eeprom_read()
1024 RAS_INDEX_TO_OFFSET(control, fri), in __amdgpu_ras_eeprom_read()
1043 int amdgpu_ras_eeprom_read_idx(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_read_idx() argument
1047 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_read_idx()
1089 * @control: pointer to control structure
1098 int amdgpu_ras_eeprom_read(struct amdgpu_ras_eeprom_control *control, in amdgpu_ras_eeprom_read() argument
1102 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_read()
1109 return amdgpu_ras_eeprom_read_idx(control, record, 0, num); in amdgpu_ras_eeprom_read()
1117 } else if (num > control->ras_num_recs) { in amdgpu_ras_eeprom_read()
1119 num, control->ras_num_recs); in amdgpu_ras_eeprom_read()
1147 g0 = control->ras_fri + num - 1; in amdgpu_ras_eeprom_read()
1148 g1 = g0 % control->ras_max_record_count; in amdgpu_ras_eeprom_read()
1149 if (g0 < control->ras_max_record_count) { in amdgpu_ras_eeprom_read()
1153 g0 = control->ras_max_record_count - control->ras_fri; in amdgpu_ras_eeprom_read()
1157 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_read()
1158 res = __amdgpu_ras_eeprom_read(control, buf, control->ras_fri, g0); in amdgpu_ras_eeprom_read()
1162 res = __amdgpu_ras_eeprom_read(control, in amdgpu_ras_eeprom_read()
1175 __decode_table_record_from_buf(control, &record[i], pp); in amdgpu_ras_eeprom_read()
1178 if ((record[i].mem_channel < BITS_PER_TYPE(control->bad_channel_bitmap)) && in amdgpu_ras_eeprom_read()
1179 !(control->bad_channel_bitmap & (1 << record[i].mem_channel))) { in amdgpu_ras_eeprom_read()
1180 control->bad_channel_bitmap |= 1 << record[i].mem_channel; in amdgpu_ras_eeprom_read()
1186 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_read()
1191 uint32_t amdgpu_ras_eeprom_max_record_count(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_max_record_count() argument
1194 amdgpu_ras_set_eeprom_table_version(control); in amdgpu_ras_eeprom_max_record_count()
1196 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in amdgpu_ras_eeprom_max_record_count()
1208 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_size_read() local
1215 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_size_read()
1219 RAS_TBL_SIZE_BYTES, control->ras_max_record_count); in amdgpu_ras_debugfs_eeprom_size_read()
1256 static loff_t amdgpu_ras_debugfs_table_size(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_debugfs_table_size() argument
1259 strlen(rec_hdr_str) + rec_hdr_fmt_size * control->ras_num_recs; in amdgpu_ras_debugfs_table_size()
1262 void amdgpu_ras_debugfs_set_ret_size(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_debugfs_set_ret_size() argument
1264 struct amdgpu_ras *ras = container_of(control, struct amdgpu_ras, in amdgpu_ras_debugfs_set_ret_size()
1269 d_inode(de)->i_size = amdgpu_ras_debugfs_table_size(control); in amdgpu_ras_debugfs_set_ret_size()
1277 struct amdgpu_ras_eeprom_control *control = &ras->eeprom_control; in amdgpu_ras_debugfs_table_read() local
1286 mutex_lock(&control->ras_tbl_mutex); in amdgpu_ras_debugfs_table_read()
1308 control->tbl_hdr.header, in amdgpu_ras_debugfs_table_read()
1309 control->tbl_hdr.version, in amdgpu_ras_debugfs_table_read()
1310 control->tbl_hdr.first_rec_offset, in amdgpu_ras_debugfs_table_read()
1311 control->tbl_hdr.tbl_size, in amdgpu_ras_debugfs_table_read()
1312 control->tbl_hdr.checksum); in amdgpu_ras_debugfs_table_read()
1338 data_len = amdgpu_ras_debugfs_table_size(control); in amdgpu_ras_debugfs_table_read()
1354 for ( ; size > 0 && s < control->ras_num_recs; s++) { in amdgpu_ras_debugfs_table_read()
1355 u32 ai = RAS_RI_TO_AI(control, s); in amdgpu_ras_debugfs_table_read()
1358 res = __amdgpu_ras_eeprom_read(control, dare, ai, 1); in amdgpu_ras_debugfs_table_read()
1361 __decode_table_record_from_buf(control, &record, dare); in amdgpu_ras_debugfs_table_read()
1364 RAS_INDEX_TO_OFFSET(control, ai), in amdgpu_ras_debugfs_table_read()
1386 mutex_unlock(&control->ras_tbl_mutex); in amdgpu_ras_debugfs_table_read()
1396 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_debugfs_eeprom_table_read() local
1403 if (!ras || !control) { in amdgpu_ras_debugfs_eeprom_table_read()
1431 * @control: pointer to control structure
1439 static int __verify_ras_table_checksum(struct amdgpu_ras_eeprom_control *control) in __verify_ras_table_checksum() argument
1441 struct amdgpu_device *adev = to_amdgpu_device(control); in __verify_ras_table_checksum()
1445 if (control->tbl_hdr.version >= RAS_TABLE_VER_V2_1) in __verify_ras_table_checksum()
1448 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in __verify_ras_table_checksum()
1451 control->ras_num_recs * RAS_TABLE_RECORD_SIZE; in __verify_ras_table_checksum()
1461 control->i2c_address + in __verify_ras_table_checksum()
1462 control->ras_header_offset, in __verify_ras_table_checksum()
1481 static int __read_table_ras_info(struct amdgpu_ras_eeprom_control *control) in __read_table_ras_info() argument
1483 struct amdgpu_ras_eeprom_table_ras_info *rai = &control->tbl_rai; in __read_table_ras_info()
1484 struct amdgpu_device *adev = to_amdgpu_device(control); in __read_table_ras_info()
1500 control->i2c_address + control->ras_info_offset, in __read_table_ras_info()
1516 static int amdgpu_ras_smu_eeprom_init(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_smu_eeprom_init() argument
1518 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_smu_eeprom_init()
1519 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_smu_eeprom_init()
1528 mutex_init(&control->ras_tbl_mutex); in amdgpu_ras_smu_eeprom_init()
1535 &(control->ras_num_recs), 100); in amdgpu_ras_smu_eeprom_init()
1544 control->ras_max_record_count = 4000; in amdgpu_ras_smu_eeprom_init()
1546 control->ras_num_mca_recs = 0; in amdgpu_ras_smu_eeprom_init()
1547 control->ras_num_pa_recs = 0; in amdgpu_ras_smu_eeprom_init()
1552 int amdgpu_ras_eeprom_init(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_init() argument
1554 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_init()
1556 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_init()
1561 return amdgpu_ras_smu_eeprom_init(control); in amdgpu_ras_eeprom_init()
1572 if (!__get_eeprom_i2c_addr(adev, control)) in amdgpu_ras_eeprom_init()
1575 control->ras_header_offset = RAS_HDR_START; in amdgpu_ras_eeprom_init()
1576 control->ras_info_offset = RAS_TABLE_V2_1_INFO_START; in amdgpu_ras_eeprom_init()
1577 mutex_init(&control->ras_tbl_mutex); in amdgpu_ras_eeprom_init()
1581 control->i2c_address + control->ras_header_offset, in amdgpu_ras_eeprom_init()
1594 return amdgpu_ras_eeprom_reset_table(control); in amdgpu_ras_eeprom_init()
1600 control->ras_num_recs = RAS_NUM_RECS_V2_1(hdr); in amdgpu_ras_eeprom_init()
1601 control->ras_record_offset = RAS_RECORD_START_V2_1; in amdgpu_ras_eeprom_init()
1602 control->ras_max_record_count = RAS_MAX_RECORD_COUNT_V2_1; in amdgpu_ras_eeprom_init()
1605 control->ras_num_recs = RAS_NUM_RECS(hdr); in amdgpu_ras_eeprom_init()
1606 control->ras_record_offset = RAS_RECORD_START; in amdgpu_ras_eeprom_init()
1607 control->ras_max_record_count = RAS_MAX_RECORD_COUNT; in amdgpu_ras_eeprom_init()
1616 if (control->ras_num_recs > control->ras_max_record_count) { in amdgpu_ras_eeprom_init()
1619 control->ras_num_recs, control->ras_max_record_count); in amdgpu_ras_eeprom_init()
1623 control->ras_fri = RAS_OFFSET_TO_INDEX(control, hdr->first_rec_offset); in amdgpu_ras_eeprom_init()
1624 control->ras_num_mca_recs = 0; in amdgpu_ras_eeprom_init()
1625 control->ras_num_pa_recs = 0; in amdgpu_ras_eeprom_init()
1629 static int amdgpu_ras_smu_eeprom_check(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_smu_eeprom_check() argument
1631 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_smu_eeprom_check()
1637 control->ras_num_bad_pages = ras->bad_page_num; in amdgpu_ras_smu_eeprom_check()
1639 if ((ras->bad_page_cnt_threshold < control->ras_num_bad_pages) && in amdgpu_ras_smu_eeprom_check()
1643 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); in amdgpu_ras_smu_eeprom_check()
1659 control->ras_num_bad_pages); in amdgpu_ras_smu_eeprom_check()
1663 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) in amdgpu_ras_smu_eeprom_check()
1665 control->ras_num_bad_pages, in amdgpu_ras_smu_eeprom_check()
1670 int amdgpu_ras_eeprom_check(struct amdgpu_ras_eeprom_control *control) in amdgpu_ras_eeprom_check() argument
1672 struct amdgpu_device *adev = to_amdgpu_device(control); in amdgpu_ras_eeprom_check()
1673 struct amdgpu_ras_eeprom_table_header *hdr = &control->tbl_hdr; in amdgpu_ras_eeprom_check()
1678 return amdgpu_ras_smu_eeprom_check(control); in amdgpu_ras_eeprom_check()
1687 if (!__get_eeprom_i2c_addr(adev, control)) in amdgpu_ras_eeprom_check()
1690 control->ras_num_bad_pages = ras->bad_page_num; in amdgpu_ras_eeprom_check()
1695 control->ras_num_bad_pages); in amdgpu_ras_eeprom_check()
1698 res = __read_table_ras_info(control); in amdgpu_ras_eeprom_check()
1703 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_check()
1713 if (10 * control->ras_num_bad_pages >= 9 * ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_check()
1715 control->ras_num_bad_pages, in amdgpu_ras_eeprom_check()
1720 res = __read_table_ras_info(control); in amdgpu_ras_eeprom_check()
1725 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_check()
1732 if (ras->bad_page_cnt_threshold >= control->ras_num_bad_pages) { in amdgpu_ras_eeprom_check()
1735 * ras->bad_page_cnt_threshold - control->num_recs > 0, in amdgpu_ras_eeprom_check()
1742 control->ras_num_bad_pages, in amdgpu_ras_eeprom_check()
1744 res = amdgpu_ras_eeprom_correct_header_tag(control, in amdgpu_ras_eeprom_check()
1749 control->ras_num_bad_pages, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_check()
1769 struct amdgpu_ras_eeprom_control *control; in amdgpu_ras_eeprom_check_and_recover() local
1775 control = &ras->eeprom_control; in amdgpu_ras_eeprom_check_and_recover()
1776 if (!control->is_eeprom_valid) in amdgpu_ras_eeprom_check_and_recover()
1778 res = __verify_ras_table_checksum(control); in amdgpu_ras_eeprom_check_and_recover()
1783 if (!amdgpu_ras_eeprom_reset_table(control)) in amdgpu_ras_eeprom_check_and_recover()
1785 if (!__verify_ras_table_checksum(control)) { in amdgpu_ras_eeprom_check_and_recover()
1790 control->is_eeprom_valid = false; in amdgpu_ras_eeprom_check_and_recover()
1937 struct amdgpu_ras_eeprom_control *control = ras ? &ras->eeprom_control : NULL; in amdgpu_ras_check_bad_page_status() local
1939 if (!control || amdgpu_bad_page_threshold == 0) in amdgpu_ras_check_bad_page_status()
1942 if (control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) { in amdgpu_ras_check_bad_page_status()