Lines Matching refs:WREG32

48 	WREG32(mmSRBM_GFX_CNTL, value);
53 	WREG32(mmSRBM_GFX_CNTL, 0);
79 	WREG32(mmSH_MEM_CONFIG, sh_mem_config);
80 	WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
81 	WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
82 	WREG32(mmSH_MEM_BASES, sh_mem_bases);
100 	WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
104 	WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
107 	WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
123 	WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK |
180 		WREG32(mmRLC_CP_SCHEDULERS, value);
187 		WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
195 		WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
196 		WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
197 		WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
201 		WREG32(reg, mqd_hqd[reg - mmCP_MQD_BASE_ADDR]);
208 	WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, data);
218 		WREG32(mmCP_HQD_PQ_WPTR, (wptr_val << wptr_shift) & wptr_mask);
221 	WREG32(mmCP_HQD_ACTIVE, data);
273 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
290 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, data);
291 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR,
295 		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR, data);
297 		WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_WPTR,
300 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_VIRTUAL_ADDR,
302 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
303 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE_HI,
305 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_LO,
307 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR_ADDR_HI,
312 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, data);
476 	WREG32(mmCP_HQD_DEQUEUE_REQUEST, type);
508 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL, temp);
521 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_DOORBELL, 0);
522 	WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_CNTL,
550 	WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
551 	WREG32(mmSQ_CMD, sq_cmd);
560 	WREG32(mmGRBM_GFX_INDEX, data);
570 	WREG32(mmSH_HIDDEN_PRIVATE_BASE_VMID, va);
581 	WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8,