86 	WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_CONFIG), sh_mem_config);  in program_sh_mem_settings_v11()
87 	WREG32(SOC15_REG_OFFSET(GC, 0, regSH_MEM_BASES), sh_mem_bases);  in program_sh_mem_settings_v11()
116 	WREG32_SOC15(GC, 0, regCPC_INT_CNTL,  in init_interrupts_v11()
187 		value = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS));  in hqd_load_v11()
190 		WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_CP_SCHEDULERS), value);  in hqd_load_v11()
195 	hqd_base = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR);  in hqd_load_v11()
198 	     reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)  in hqd_load_v11()
205 	WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), data);  in hqd_load_v11()
234 		WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_LO),  in hqd_load_v11()
236 		WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI),  in hqd_load_v11()
238 		WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR),  in hqd_load_v11()
240 		WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI),  in hqd_load_v11()
244 		WREG32(SOC15_REG_OFFSET(GC, 0, regCP_PQ_WPTR_POLL_CNTL1),  in hqd_load_v11()
249 	WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_EOP_RPTR),  in hqd_load_v11()
254 	WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE), data);  in hqd_load_v11()
332 	for (reg = SOC15_REG_OFFSET(GC, 0, regCP_MQD_BASE_ADDR);  in hqd_dump_v11()
333 	     reg <= SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_WPTR_HI); reg++)  in hqd_dump_v11()
457 	act = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE));  in hqd_is_occupied_v11()
462 		if (low == RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_BASE)) &&  in hqd_is_occupied_v11()
463 		   high == RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_BASE_HI)))  in hqd_is_occupied_v11()
501 		WREG32_FIELD15_PREREG(GC, 0, RLC_CP_SCHEDULERS, scheduler1, 0);  in hqd_destroy_v11()
515 	WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_DEQUEUE_REQUEST), type);  in hqd_destroy_v11()
519 		temp = RREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_ACTIVE));  in hqd_destroy_v11()
582 	WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), gfx_index_val);  in wave_control_execute_v11()
583 	WREG32(SOC15_REG_OFFSET(GC, 0, regSQ_CMD), sq_cmd);  in wave_control_execute_v11()
592 	WREG32(SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX), data);  in wave_control_execute_v11()
772 	WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_H) +  in kgd_gfx_v11_set_address_watch()
776 	WREG32_RLC((SOC15_REG_OFFSET(GC, 0, regTCP_WATCH0_ADDR_L) +  in kgd_gfx_v11_set_address_watch()