amd/amdgpu/amdgpu_aca.c

39 static void aca_banks_init(struct aca_banks *banks)
41 	if (!banks)
44 	memset(banks, 0, sizeof(*banks));
45 	INIT_LIST_HEAD(&banks->list);
48 static int aca_banks_add_bank(struct aca_banks *banks, struct aca_bank *bank)
62 	list_add_tail(&node->node, &banks->list);
64 	banks->nr_banks++;
69 static void aca_banks_release(struct aca_banks *banks)
73 	if (list_empty(&banks->list))
76 	list_for_each_entry_safe(node, tmp, &banks->list, node) {
135 				       struct aca_banks *banks, struct ras_query_context *qctx)
173 		ret = aca_banks_add_bank(banks, &bank);
354 static int aca_dispatch_banks(struct aca_handle_manager *mgr, struct aca_banks *banks,
361 	if (!mgr || !banks)
365 	if (list_empty(&mgr->list) || list_empty(&banks->list))
368 	list_for_each_entry(node, &banks->list, node) {
401 				    struct aca_banks *banks,
411 	if (!banks || !count) {
421 		list_for_each_entry(node, &banks->list, node) {
426 					dev_warn(adev->dev, "fail to add de banks, ret = %d\n", r);
441 		 * SMU_TYPE_CE banks are combined into 1 CPER entries,
444 		if (amdgpu_cper_generate_ce_records(adev, banks, count))
453 	struct aca_banks banks;
470 	aca_banks_init(&banks);
472 	ret = aca_smu_get_valid_aca_banks(adev, type, 0, count, &banks, qctx);
476 	if (list_empty(&banks.list)) {
481 	ret = aca_dispatch_banks(&aca->mgr, &banks, type,
486 	aca_banks_generate_cper(adev, type, &banks, count);
489 	aca_banks_release(&banks);