drivers/gpio/gpio-ftgpio010.c

57 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
59 	writel(BIT(irqd_to_hwirq(d)), g->base + GPIO_INT_CLR);
65 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
68 	val = readl(g->base + GPIO_INT_EN);
70 	writel(val, g->base + GPIO_INT_EN);
77 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
81 	val = readl(g->base + GPIO_INT_EN);
83 	writel(val, g->base + GPIO_INT_EN);
89 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
93 	reg_type = readl(g->base + GPIO_INT_TYPE);
94 	reg_level = readl(g->base + GPIO_INT_LEVEL);
95 	reg_both = readl(g->base + GPIO_INT_BOTH_EDGE);
130 	writel(reg_type, g->base + GPIO_INT_TYPE);
131 	writel(reg_level, g->base + GPIO_INT_LEVEL);
132 	writel(reg_both, g->base + GPIO_INT_BOTH_EDGE);
142 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
149 	stat = readl(g->base + GPIO_INT_STAT_RAW);
162 	struct ftgpio_gpio *g = gpiochip_get_data(gc);
181 	pclk_freq = clk_get_rate(g->clk);
188 	dev_dbg(g->dev, "prescale divisor: %08x, resulting frequency %lu Hz\n",
191 	val = readl(g->base + GPIO_DEBOUNCE_PRESCALE);
200 		val = readl(g->base + GPIO_DEBOUNCE_EN);
202 		writel(val, g->base + GPIO_DEBOUNCE_EN);
206 	val = readl(g->base + GPIO_DEBOUNCE_EN);
216 	writel(deb_div, g->base + GPIO_DEBOUNCE_PRESCALE);
219 	writel(val, g->base + GPIO_DEBOUNCE_EN);
237 	struct ftgpio_gpio *g;
242 	g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
243 	if (!g)
246 	g->dev = dev;
248 	g->base = devm_platform_ioremap_resource(pdev, 0);
249 	if (IS_ERR(g->base))
250 		return PTR_ERR(g->base);
256 	g->clk = devm_clk_get_enabled(dev, NULL);
257 	if (IS_ERR(g->clk) && PTR_ERR(g->clk) == -EPROBE_DEFER)
262 		return PTR_ERR(g->clk);
264 	ret = bgpio_init(&g->gc, dev, 4,
265 			 g->base + GPIO_DATA_IN,
266 			 g->base + GPIO_DATA_SET,
267 			 g->base + GPIO_DATA_CLR,
268 			 g->base + GPIO_DIR,
274 	g->gc.label = dev_name(dev);
275 	g->gc.base = -1;
276 	g->gc.parent = dev;
277 	g->gc.owner = THIS_MODULE;
281 	if (!IS_ERR(g->clk))
282 		g->gc.set_config = ftgpio_gpio_set_config;
284 	girq = &g->gc.irq;
298 	writel(0x0, g->base + GPIO_INT_EN);
299 	writel(0x0, g->base + GPIO_INT_MASK);
300 	writel(~0x0, g->base + GPIO_INT_CLR);
303 	writel(0x0, g->base + GPIO_DEBOUNCE_EN);
305 	return devm_gpiochip_add_data(dev, &g->gc, g);