Lines Matching full:pvt
396 #define CH_ACTIVE(pvt, ch) ((pvt)->info.mc_control & (1 << (8 + ch)))
397 #define ECCx8(pvt) ((pvt)->info.mc_control & (1 << 1))
400 #define ECC_ENABLED(pvt) ((pvt)->info.mc_status & (1 << 4))
401 #define CH_DISABLED(pvt, ch) ((pvt)->info.mc_status & (1 << ch))
489 struct i7core_pvt *pvt = mci->pvt_info;
497 pdev = pvt->pci_mcr[0];
502 pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
503 pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
504 pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
505 pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
508 pvt->i7core_dev->socket, pvt->info.mc_control,
509 pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map);
511 if (ECC_ENABLED(pvt)) {
512 edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
513 if (ECCx8(pvt))
524 numdimms(pvt->info.max_dod),
525 numrank(pvt->info.max_dod >> 2),
526 numbank(pvt->info.max_dod >> 4),
527 numrow(pvt->info.max_dod >> 6),
528 numcol(pvt->info.max_dod >> 9));
533 if (!pvt->pci_ch[i][0])
536 if (!CH_ACTIVE(pvt, i)) {
540 if (CH_DISABLED(pvt, i)) {
546 pci_read_config_dword(pvt->pci_ch[i][0],
551 pvt->channel[i].is_3dimms_present = true;
554 pvt->channel[i].is_single_4rank = true;
557 pvt->channel[i].has_4rank = true;
565 pci_read_config_dword(pvt->pci_ch[i][1],
567 pci_read_config_dword(pvt->pci_ch[i][1],
569 pci_read_config_dword(pvt->pci_ch[i][1],
574 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
576 pvt->channel[i].is_3dimms_present ? "3DIMMS " : "",
577 pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "",
578 pvt->channel[i].has_4rank ? "HAS_4R " : "",
622 pvt->i7core_dev->socket, i, j);
662 struct i7core_pvt *pvt = mci->pvt_info;
664 pvt->inject.enable = 0;
666 if (!pvt->pci_ch[pvt->inject.channel][0])
669 pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
687 struct i7core_pvt *pvt = mci->pvt_info;
691 if (pvt->inject.enable)
698 pvt->inject.section = (u32) value;
707 struct i7core_pvt *pvt = mci->pvt_info;
708 return sprintf(data, "0x%08x\n", pvt->inject.section);
724 struct i7core_pvt *pvt = mci->pvt_info;
728 if (pvt->inject.enable)
735 pvt->inject.type = (u32) value;
744 struct i7core_pvt *pvt = mci->pvt_info;
746 return sprintf(data, "0x%08x\n", pvt->inject.type);
764 struct i7core_pvt *pvt = mci->pvt_info;
768 if (pvt->inject.enable)
775 pvt->inject.eccmask = (u32) value;
784 struct i7core_pvt *pvt = mci->pvt_info;
786 return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
807 struct i7core_pvt *pvt; \
812 pvt = mci->pvt_info; \
814 if (pvt->inject.enable) \
825 pvt->inject.param = value; \
836 struct i7core_pvt *pvt; \
838 pvt = mci->pvt_info; \
839 edac_dbg(1, "pvt=%p\n", pvt); \
840 if (pvt->inject.param < 0) \
843 return sprintf(data, "%d\n", pvt->inject.param);\
915 struct i7core_pvt *pvt = mci->pvt_info;
921 if (!pvt->pci_ch[pvt->inject.channel][0])
929 pvt->inject.enable = 1;
935 /* Sets pvt->inject.dimm mask */
936 if (pvt->inject.dimm < 0)
939 if (pvt->channel[pvt->inject.channel].dimms > 2)
940 mask |= (pvt->inject.dimm & 0x3LL) << 35;
942 mask |= (pvt->inject.dimm & 0x1LL) << 36;
945 /* Sets pvt->inject.rank mask */
946 if (pvt->inject.rank < 0)
949 if (pvt->channel[pvt->inject.channel].dimms > 2)
950 mask |= (pvt->inject.rank & 0x1LL) << 34;
952 mask |= (pvt->inject.rank & 0x3LL) << 34;
955 /* Sets pvt->inject.bank mask */
956 if (pvt->inject.bank < 0)
959 mask |= (pvt->inject.bank & 0x15LL) << 30;
961 /* Sets pvt->inject.page mask */
962 if (pvt->inject.page < 0)
965 mask |= (pvt->inject.page & 0xffff) << 14;
967 /* Sets pvt->inject.column mask */
968 if (pvt->inject.col < 0)
971 mask |= (pvt->inject.col & 0x3fff);
980 injectmask = (pvt->inject.type & 1) |
981 (pvt->inject.section & 0x3) << 1 |
982 (pvt->inject.type & 0x6) << (3 - 1);
985 pci_write_config_dword(pvt->pci_noncore,
988 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
990 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
993 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
994 MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
996 write_and_test(pvt->pci_ch[pvt->inject.channel][0],
1004 pci_write_config_dword(pvt->pci_noncore,
1008 mask, pvt->inject.eccmask, injectmask);
1019 struct i7core_pvt *pvt = mci->pvt_info;
1022 if (!pvt->pci_ch[pvt->inject.channel][0])
1025 pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
1031 pvt->inject.enable = 1;
1033 return sprintf(data, "%d\n", pvt->inject.enable);
1043 struct i7core_pvt *pvt = mci->pvt_info; \
1046 if (!pvt->ce_count_available || (pvt->is_registered)) \
1049 pvt->udimm_ce_count[param]); \
1159 struct i7core_pvt *pvt = mci->pvt_info;
1162 pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL);
1163 if (!pvt->addrmatch_dev)
1166 pvt->addrmatch_dev->type = &addrmatch_type;
1167 pvt->addrmatch_dev->bus = mci->dev.bus;
1168 device_initialize(pvt->addrmatch_dev);
1169 pvt->addrmatch_dev->parent = &mci->dev;
1170 dev_set_name(pvt->addrmatch_dev, "inject_addrmatch");
1171 dev_set_drvdata(pvt->addrmatch_dev, mci);
1173 edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev));
1175 rc = device_add(pvt->addrmatch_dev);
1179 if (!pvt->is_registered) {
1180 pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev),
1182 if (!pvt->chancounts_dev) {
1187 pvt->chancounts_dev->type = &all_channel_counts_type;
1188 pvt->chancounts_dev->bus = mci->dev.bus;
1189 device_initialize(pvt->chancounts_dev);
1190 pvt->chancounts_dev->parent = &mci->dev;
1191 dev_set_name(pvt->chancounts_dev, "all_channel_counts");
1192 dev_set_drvdata(pvt->chancounts_dev, mci);
1194 edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev));
1196 rc = device_add(pvt->chancounts_dev);
1203 put_device(pvt->chancounts_dev);
1205 device_del(pvt->addrmatch_dev);
1207 put_device(pvt->addrmatch_dev);
1214 struct i7core_pvt *pvt = mci->pvt_info;
1218 if (!pvt->is_registered) {
1219 device_del(pvt->chancounts_dev);
1220 put_device(pvt->chancounts_dev);
1222 device_del(pvt->addrmatch_dev);
1223 put_device(pvt->addrmatch_dev);
1455 struct i7core_pvt *pvt = mci->pvt_info;
1460 pvt->is_registered = false;
1461 pvt->enable_scrub = false;
1472 pvt->pci_mcr[func] = pdev;
1476 pvt->pci_ch[slot - 4][func] = pdev;
1478 pvt->pci_noncore = pdev;
1484 pvt->enable_scrub = false;
1488 pvt->enable_scrub = false;
1492 pvt->enable_scrub = false;
1496 pvt->enable_scrub = true;
1500 pvt->enable_scrub = true;
1504 pvt->enable_scrub = false;
1516 pvt->is_registered = true;
1538 struct i7core_pvt *pvt = mci->pvt_info;
1541 if (pvt->ce_count_available) {
1544 add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
1545 add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
1546 add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
1550 pvt->rdimm_ce_count[chan][2] += add2;
1554 pvt->rdimm_ce_count[chan][1] += add1;
1558 pvt->rdimm_ce_count[chan][0] += add0;
1560 pvt->ce_count_available = 1;
1563 pvt->rdimm_last_ce_count[chan][2] = new2;
1564 pvt->rdimm_last_ce_count[chan][1] = new1;
1565 pvt->rdimm_last_ce_count[chan][0] = new0;
1584 struct i7core_pvt *pvt = mci->pvt_info;
1589 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
1591 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
1593 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
1595 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
1597 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
1599 pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
1605 if (pvt->channel[i].dimms > 2) {
1629 struct i7core_pvt *pvt = mci->pvt_info;
1633 if (!pvt->pci_mcr[4]) {
1639 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
1640 pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
1648 if (pvt->ce_count_available) {
1652 add2 = new2 - pvt->udimm_last_ce_count[2];
1653 add1 = new1 - pvt->udimm_last_ce_count[1];
1654 add0 = new0 - pvt->udimm_last_ce_count[0];
1658 pvt->udimm_ce_count[2] += add2;
1662 pvt->udimm_ce_count[1] += add1;
1666 pvt->udimm_ce_count[0] += add0;
1673 pvt->ce_count_available = 1;
1676 pvt->udimm_last_ce_count[2] = new2;
1677 pvt->udimm_last_ce_count[1] = new1;
1678 pvt->udimm_last_ce_count[0] = new0;
1697 struct i7core_pvt *pvt = mci->pvt_info;
1778 if (uncorrected_error || !pvt->is_registered)
1793 struct i7core_pvt *pvt = mci->pvt_info;
1800 if (!pvt->is_registered)
1959 struct i7core_pvt *pvt = mci->pvt_info;
1965 pdev = pvt->pci_mcr[2];
1984 const u32 freq_dclk_mhz = pvt->dclk_freq;
2021 struct i7core_pvt *pvt = mci->pvt_info;
2024 const u32 freq_dclk_mhz = pvt->dclk_freq;
2029 pdev = pvt->pci_mcr[2];
2050 struct i7core_pvt *pvt = mci->pvt_info;
2054 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2056 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2065 struct i7core_pvt *pvt = mci->pvt_info;
2069 pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
2071 pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
2075 static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
2077 pvt->i7core_pci = edac_pci_create_generic_ctl(
2078 &pvt->i7core_dev->pdev[0]->dev,
2080 if (unlikely(!pvt->i7core_pci))
2085 static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
2087 if (likely(pvt->i7core_pci))
2088 edac_pci_release_generic_ctl(pvt->i7core_pci);
2092 pvt->i7core_dev->socket);
2093 pvt->i7core_pci = NULL;
2099 struct i7core_pvt *pvt;
2108 pvt = mci->pvt_info;
2113 if (pvt->enable_scrub)
2117 i7core_pci_ctl_release(pvt);
2132 struct i7core_pvt *pvt;
2145 sizeof(*pvt));
2151 pvt = mci->pvt_info;
2152 memset(pvt, 0, sizeof(*pvt));
2155 pvt->i7core_dev = i7core_dev;
2189 if (pvt->enable_scrub)
2210 pvt->inject.channel = 0;
2211 pvt->inject.dimm = -1;
2212 pvt->inject.rank = -1;
2213 pvt->inject.bank = -1;
2214 pvt->inject.page = -1;
2215 pvt->inject.col = -1;
2218 i7core_pci_ctl_create(pvt);
2221 pvt->dclk_freq = get_dclk_freq();