Lines Matching full:pvt

178 static u32 dmc520_read_reg(struct dmc520_edac *pvt, u32 offset)
180 	return readl(pvt->reg_base + offset);
183 static void dmc520_write_reg(struct dmc520_edac *pvt, u32 val, u32 offset)
185 	writel(val, pvt->reg_base + offset);
200 static u32 dmc520_get_dram_ecc_error_count(struct dmc520_edac *pvt,
212 	err_low = dmc520_read_reg(pvt, reg_offset_low);
213 	err_high = dmc520_read_reg(pvt, reg_offset_high);
215 	dmc520_write_reg(pvt, 0, reg_offset_low);
216 	dmc520_write_reg(pvt, 0, reg_offset_high);
224 static void dmc520_get_dram_ecc_error_info(struct dmc520_edac *pvt,
237 	reg_val_low = dmc520_read_reg(pvt, reg_offset_low);
238 	reg_val_high = dmc520_read_reg(pvt, reg_offset_high);
260 static enum scrub_type dmc520_get_scrub_type(struct dmc520_edac *pvt)
265 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW);
276 static u32 dmc520_get_memory_width(struct dmc520_edac *pvt)
282 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL);
292 static enum mem_type dmc520_get_mtype(struct dmc520_edac *pvt)
298 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);
314 static enum dev_type dmc520_get_dtype(struct dmc520_edac *pvt)
320 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW);
350 static u64 dmc520_get_rank_size(struct dmc520_edac *pvt)
354 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_ADDRESS_CONTROL_NOW);
362 	return (u64)pvt->mem_width_in_bytes << (col_bits + row_bits + bank_bits);
368 	struct dmc520_edac *pvt = mci->pvt_info;
373 	dmc520_get_dram_ecc_error_info(pvt, is_ce, &info);
375 	cnt = dmc520_get_dram_ecc_error_count(pvt, is_ce);
384 	spin_lock(&pvt->error_lock);
389 	spin_unlock(&pvt->error_lock);
395 	struct dmc520_edac *pvt = mci->pvt_info;
402 	dmc520_write_reg(pvt, i_mask, REG_OFFSET_INTERRUPT_CLR);
410 	struct dmc520_edac *pvt = mci->pvt_info;
414 	status = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_STATUS);
430 	struct dmc520_edac *pvt = mci->pvt_info;
435 		if (pvt->irqs[idx] == irq) {
436 			mask = pvt->masks[idx];
445 	struct dmc520_edac *pvt = mci->pvt_info;
454 	dt = dmc520_get_dtype(pvt);
455 	mt = dmc520_get_mtype(pvt);
456 	rs = dmc520_get_rank_size(pvt);
464 			dimm->grain	= pvt->mem_width_in_bytes;
479 	struct dmc520_edac *pvt = NULL;
518 	mci = edac_mc_alloc(dmc520_mc_idx++, ARRAY_SIZE(layers), layers, sizeof(*pvt));
526 	pvt = mci->pvt_info;
528 	pvt->reg_base = reg_base;
529 	spin_lock_init(&pvt->error_lock);
530 	memcpy(pvt->irqs, irqs, sizeof(irqs));
531 	memcpy(pvt->masks, masks, sizeof(masks));
540 	mci->scrub_mode		= dmc520_get_scrub_type(pvt);
547 	pvt->mem_width_in_bytes = dmc520_get_memory_width(pvt);
552 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);
553 	dmc520_write_reg(pvt, reg_val & (~irq_mask_all),
555 	dmc520_write_reg(pvt, irq_mask_all, REG_OFFSET_INTERRUPT_CLR);
574 		dmc520_get_dram_ecc_error_count(pvt, true);
577 		dmc520_get_dram_ecc_error_count(pvt, false);
587 	dmc520_write_reg(pvt, reg_val | irq_mask_all,
595 			devm_free_irq(&pdev->dev, pvt->irqs[idx], mci);
607 	struct dmc520_edac *pvt;
610 	pvt = mci->pvt_info;
613 	reg_val = dmc520_read_reg(pvt, REG_OFFSET_INTERRUPT_CONTROL);
614 	dmc520_write_reg(pvt, reg_val & (~irq_mask_all),
619 		if (pvt->irqs[idx] >= 0) {
620 			irq_mask_all |= pvt->masks[idx];
621 			devm_free_irq(&pdev->dev, pvt->irqs[idx], mci);