Lines Matching full:and
4 # Licensed and distributed under the GPL
13 tristate "EDAC (Error Detection And Correction) reporting"
40 levels are 0-4 (from low to high) and by default it is set to 2.
69 It should be noticed that keeping both GHES and a hardware-driven
81 The EDAC scrub feature is optional and is designed to control the
90 The EDAC ECS feature is optional and is designed to control on-die
99 The EDAC memory repair feature is optional and is designed to control
112 Support for error detection and correction of DRAM ECC errors on
118 AMD CPUs up to and excluding family 0x17 provide for Memory
120 module allows the operator/user to inject Uncorrectable and
130 In addition, there are two control files, inject_read and inject_write,
131 which trigger the DRAM ECC Read and Write respectively.
137 Support for error detection and correction for Amazon's Annapurna
138 Labs Alpine chips which allow 1 bit correction and 2 bits detection.
144 Support for error detection and correction on the AMD 76x
151 Support for error detection and correction on the Intel
152 E7205, E7500, E7501 and E7505 server chipsets.
155 tristate "Intel e752x (e7520, e7525, e7320) and 3100"
158 Support for error detection and correction on the Intel
166 Support for error detection and correction on the Intel
173 Support for error detection and correction on the Intel
174 DP82785P and E7210 server chipsets.
180 Support for error detection and correction on the Intel
187 Support for error detection and correction on the Intel
188 3000 and 3010 server chipsets.
194 Support for error detection and correction on the Intel
195 3200 and 3210 server chipsets.
201 Support for error detection and correction on the Intel
208 Support for error detection and correction on the Intel
215 Support for error detection and correction the Intel
222 Support for error detection and correction the Intel
225 and Xeon 55xx processors.
231 Support for error detection and correction on the Intel
238 Support for error detection and correction on the Radisys
246 Support for error detection and correction the Intel
253 Support for error detection and correction the Intel
260 Support for error detection and correction the Intel
267 Support for error detection and correction the Intel
268 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
277 Support for error detection and correction the Intel
289 Support for error detection and correction the Intel
299 Support for error detection and correction on the Intel
301 first used on the Apollo Lake platform and Denverton
309 Support for error detection and correction on the Intel
318 Support for error detection and correction on the Freescale
325 Support for error detection and correction on Freescale memory
332 Support for error detection and correction on PA Semi
339 Support for error detection and correction on the
340 IBM CPC925 Bridge and Memory Controller, which is
348 Support for error detection and correction on the
355 Support for error detection and correction on the
362 Support for error detection and correction on the primary caches of
369 Support for error detection and correction on the
376 Support for error detection and correction on the
383 Support for error detection and correction on the
391 Support for error detection and correction on the
393 Coherent Processor Interconnect (CCPI) and L2 cache
400 Support for error detection and correction on the
408 Support for error detection and correction on the
417 Support for error detection and correction on the
425 Support for error detection and correction on the
432 Support for error detection and correction on the
439 Support for error detection and correction on the
446 Support for error detection and correction on the
453 Support for error detection and correction on the
460 Support for error detection and correction on the
467 Support for error detection and correction on the
474 Support for error detection and correction on the SiFive SoCs.
477 bool "Marvell Armada XP DDR and L2 Cache ECC"
480 Support for error correction and detection on the Marvell Aramada XP
481 DDR RAM and L2 cache controllers.
487 Support for error detection and correction on the Synopsys DDR
494 Support for error detection and correction on the
501 Support for error detection and correction on the TI SoCs.
507 Support for error detection and correction on the
510 This driver reports Single Bit Errors (SBEs) and Double Bit Errors (DBEs).
512 of Tag RAM and Data RAM.
514 For debugging issues having to do with stability and overall system
521 Support for error detection and correction on the Aspeed AST BMC SoC.
530 Support for error detection and correction on the
537 Support for error detection and correction on the
544 This driver supports error detection and correction for the
552 Support for error detection and correction on the Nuvoton NPCM DDR
563 Support for error detection and correction on the Xilinx Versal DDR
566 Report both single bit errors (CE) and double bit errors (UE).
567 Support injecting both correctable and uncorrectable errors
574 Support for error detection and correction on the Loongson