Lines Matching defs:pin
28 * struct zl3073x_dpll_pin - DPLL pin
29 * @list: this DPLL pin list entry
30 * @dpll: DPLL the pin is registered to
33 * @dir: pin direction
34 * @id: pin id
35 * @prio: pin priority <0, 14>
36 * @selectable: pin is selectable in automatic mode
38 * @pin_state: last saved pin state
39 * @phase_offset: last saved pin phase offset
65 * zl3073x_dpll_is_input_pin - check if the pin is input one
66 * @pin: pin to check
68 * Return: true if pin is input, false if pin is output.
71 zl3073x_dpll_is_input_pin(struct zl3073x_dpll_pin *pin)
73 return pin->dir == DPLL_PIN_DIRECTION_INPUT;
77 * zl3073x_dpll_is_p_pin - check if the pin is P-pin
78 * @pin: pin to check
80 * Return: true if the pin is P-pin, false if it is N-pin
83 zl3073x_dpll_is_p_pin(struct zl3073x_dpll_pin *pin)
85 return zl3073x_is_p_pin(pin->id);
94 struct zl3073x_dpll_pin *pin = pin_priv;
96 *direction = pin->dir;
165 struct zl3073x_dpll_pin *pin = pin_priv;
171 ref = zl3073x_input_pin_ref_get(pin->id);
172 rc = zl3073x_dpll_input_ref_frequency_get(zldpll, pin->id, &ref_freq);
207 /* If the pin supports esync control expose its range but only
210 if (pin->esync_control && ref_freq > 1) {
230 struct zl3073x_dpll_pin *pin = pin_priv;
237 ref = zl3073x_input_pin_ref_get(pin->id);
280 struct zl3073x_dpll_pin *pin = pin_priv;
282 *ffo = pin->freq_offset;
295 struct zl3073x_dpll_pin *pin = pin_priv;
301 ref = zl3073x_input_pin_ref_get(pin->id);
318 struct zl3073x_dpll_pin *pin = pin_priv;
331 ref = zl3073x_input_pin_ref_get(pin->id);
524 struct zl3073x_dpll_pin *pin = pin_priv;
534 /* Report phase offset only for currently connected pin if the phase
537 ref = zl3073x_input_pin_ref_get(pin->id);
544 /* Get this pin monitor status */
549 /* Report phase offset only if the input pin signal is present */
556 ref_phase = pin->phase_offset;
601 struct zl3073x_dpll_pin *pin = pin_priv;
609 ref = zl3073x_input_pin_ref_get(pin->id);
641 struct zl3073x_dpll_pin *pin = pin_priv;
654 ref = zl3073x_input_pin_ref_get(pin->id);
671 * zl3073x_dpll_ref_prio_get - get priority for given input pin
672 * @pin: pointer to pin
675 * Reads current priority for the given input pin and stores the value
681 zl3073x_dpll_ref_prio_get(struct zl3073x_dpll_pin *pin, u8 *prio)
683 struct zl3073x_dpll *zldpll = pin->dpll;
696 /* Read reference priority - one value for P&N pins (4 bits/pin) */
697 ref = zl3073x_input_pin_ref_get(pin->id);
703 /* Select nibble according pin type */
704 if (zl3073x_dpll_is_p_pin(pin))
713 * zl3073x_dpll_ref_prio_set - set priority for given input pin
714 * @pin: pointer to pin
717 * Sets priority for the given input pin.
722 zl3073x_dpll_ref_prio_set(struct zl3073x_dpll_pin *pin, u8 prio)
724 struct zl3073x_dpll *zldpll = pin->dpll;
738 ref = zl3073x_input_pin_ref_get(pin->id);
743 /* Update nibble according pin type */
744 if (zl3073x_dpll_is_p_pin(pin)) {
763 * zl3073x_dpll_ref_state_get - get status for given input pin
764 * @pin: pointer to pin
767 * Checks current status for the given input pin and stores the value
773 zl3073x_dpll_ref_state_get(struct zl3073x_dpll_pin *pin,
776 struct zl3073x_dpll *zldpll = pin->dpll;
781 ref = zl3073x_input_pin_ref_get(pin->id);
795 * pin as selectable.
798 pin->selectable) {
814 /* Otherwise report the pin as disconnected */
828 struct zl3073x_dpll_pin *pin = pin_priv;
830 return zl3073x_dpll_ref_state_get(pin, state);
842 struct zl3073x_dpll_pin *pin = pin_priv;
851 /* Choose the pin as new selected reference */
852 new_ref = zl3073x_input_pin_ref_get(pin->id);
858 "Invalid pin state for manual mode");
867 if (pin->selectable)
870 /* Restore pin priority in HW */
871 rc = zl3073x_dpll_ref_prio_set(pin, pin->prio);
875 /* Mark pin as selectable */
876 pin->selectable = true;
878 if (!pin->selectable)
881 /* Set pin priority to none in HW */
882 rc = zl3073x_dpll_ref_prio_set(pin,
887 /* Mark pin as non-selectable */
888 pin->selectable = false;
891 "Invalid pin state for automatic mode");
912 struct zl3073x_dpll_pin *pin = pin_priv;
914 *prio = pin->prio;
924 struct zl3073x_dpll_pin *pin = pin_priv;
930 /* If the pin is selectable then update HW registers */
931 if (pin->selectable) {
932 rc = zl3073x_dpll_ref_prio_set(pin, prio);
938 pin->prio = prio;
953 struct zl3073x_dpll_pin *pin = pin_priv;
962 out = zl3073x_output_pin_out_get(pin->id);
1001 /* Get synth attached to output pin */
1044 /* Set supported esync ranges if the pin supports esync control and
1047 if (pin->esync_control && (synth_freq / output_div) > 1) {
1068 struct zl3073x_dpll_pin *pin = pin_priv;
1073 out = zl3073x_output_pin_out_get(pin->id);
1117 /* Get synth attached to output pin */
1166 struct zl3073x_dpll_pin *pin = pin_priv;
1172 out = zl3073x_output_pin_out_get(pin->id);
1202 * given output pin type.
1204 if (zl3073x_dpll_is_p_pin(pin)) {
1205 /* For P-pin the resulting frequency is computed as
1211 /* For N-pin we have to divide additionally by
1213 * register that is used as N-pin divisor for these
1223 /* Check N-pin divisor for zero */
1226 "Zero N-pin divisor for output %u got from device\n",
1231 /* Compute final divisor for N-pin */
1255 struct zl3073x_dpll_pin *pin = pin_priv;
1263 out = zl3073x_output_pin_out_get(pin->id);
1312 /* Get N-pin divisor (shares the same register with esync */
1317 /* Check N-pin divisor for zero */
1320 "Zero N-pin divisor for output %u got from device\n",
1325 /* Compute current output frequency for P-pin */
1328 /* Compute current N-pin frequency */
1331 if (zl3073x_dpll_is_p_pin(pin)) {
1332 /* We are going to change output frequency for P-pin but
1333 * if the requested frequency is less than current N-pin
1335 * to compute N-pin divisor to keep its frequency unchanged.
1350 /* Compute new divisor for N-pin */
1353 /* We are going to change frequency of N-pin but if
1354 * the requested freq is greater or equal than freq of P-pin
1355 * in the output pair we cannot compute divisor for the N-pin.
1361 /* Compute new divisor for N-pin */
1365 /* Update divisor for the N-pin */
1390 struct zl3073x_dpll_pin *pin = pin_priv;
1396 out = zl3073x_output_pin_out_get(pin->id);
1439 struct zl3073x_dpll_pin *pin = pin_priv;
1446 out = zl3073x_output_pin_out_get(pin->id);
1496 /* If the output pin is registered then it is always connected */
1643 * zl3073x_dpll_pin_alloc - allocate DPLL pin
1645 * @dir: pin direction
1646 * @id: pin id
1649 * pin id and direction.
1657 struct zl3073x_dpll_pin *pin;
1659 pin = kzalloc(sizeof(*pin), GFP_KERNEL);
1660 if (!pin)
1663 pin->dpll = zldpll;
1664 pin->dir = dir;
1665 pin->id = id;
1667 return pin;
1671 * zl3073x_dpll_pin_free - deallocate DPLL pin
1672 * @pin: pin to free
1674 * Deallocates DPLL pin previously allocated by @zl3073x_dpll_pin_alloc.
1677 zl3073x_dpll_pin_free(struct zl3073x_dpll_pin *pin)
1679 WARN(pin->dpll_pin, "DPLL pin is still registered\n");
1681 kfree(pin);
1685 * zl3073x_dpll_pin_register - register DPLL pin
1686 * @pin: pointer to DPLL pin
1687 * @index: absolute pin index for registration
1689 * Registers given DPLL pin into DPLL sub-system.
1694 zl3073x_dpll_pin_register(struct zl3073x_dpll_pin *pin, u32 index)
1696 struct zl3073x_dpll *zldpll = pin->dpll;
1701 /* Get pin properties */
1702 props = zl3073x_pin_props_get(zldpll->dev, pin->dir, pin->id);
1707 strscpy(pin->label, props->package_label);
1708 pin->esync_control = props->esync_control;
1710 if (zl3073x_dpll_is_input_pin(pin)) {
1711 rc = zl3073x_dpll_ref_prio_get(pin, &pin->prio);
1715 if (pin->prio == ZL_DPLL_REF_PRIO_NONE) {
1716 /* Clamp prio to max value & mark pin non-selectable */
1717 pin->prio = ZL_DPLL_REF_PRIO_MAX;
1718 pin->selectable = false;
1720 /* Mark pin as selectable */
1721 pin->selectable = true;
1725 /* Create or get existing DPLL pin */
1726 pin->dpll_pin = dpll_pin_get(zldpll->dev->clock_id, index, THIS_MODULE,
1728 if (IS_ERR(pin->dpll_pin)) {
1729 rc = PTR_ERR(pin->dpll_pin);
1733 if (zl3073x_dpll_is_input_pin(pin))
1738 /* Register the pin */
1739 rc = dpll_pin_register(zldpll->dpll_dev, pin->dpll_pin, ops, pin);
1743 /* Free pin properties */
1749 dpll_pin_put(pin->dpll_pin);
1751 pin->dpll_pin = NULL;
1759 * zl3073x_dpll_pin_unregister - unregister DPLL pin
1760 * @pin: pointer to DPLL pin
1762 * Unregisters pin previously registered by @zl3073x_dpll_pin_register.
1765 zl3073x_dpll_pin_unregister(struct zl3073x_dpll_pin *pin)
1767 struct zl3073x_dpll *zldpll = pin->dpll;
1770 WARN(!pin->dpll_pin, "DPLL pin is not registered\n");
1772 if (zl3073x_dpll_is_input_pin(pin))
1777 /* Unregister the pin */
1778 dpll_pin_unregister(zldpll->dpll_dev, pin->dpll_pin, ops, pin);
1780 dpll_pin_put(pin->dpll_pin);
1781 pin->dpll_pin = NULL;
1794 struct zl3073x_dpll_pin *pin, *next;
1796 list_for_each_entry_safe(pin, next, &zldpll->pins, list) {
1797 zl3073x_dpll_pin_unregister(pin);
1798 list_del(&pin->list);
1799 zl3073x_dpll_pin_free(pin);
1804 * zl3073x_dpll_pin_is_registrable - check if the pin is registrable
1806 * @dir: pin direction
1807 * @index: pin index
1809 * Checks if the given pin can be registered to given DPLL. For both
1810 * directions the pin can be registered if it is enabled. In case of
1811 * differential signal type only P-pin is reported as registrable.
1812 * And additionally for the output pin, the pin can be registered only
1815 * Return: true if the pin is registrable, false if not
1830 /* Skip the pin if the DPLL is running in NCO mode */
1842 /* Skip the pin if it is connected to different DPLL channel */
1855 /* Skip N-pin if the corresponding input/output is differential */
1857 dev_dbg(zldev->dev, "%s%u is differential, skipping N-pin\n",
1863 /* Skip the pin if it is disabled */
1886 struct zl3073x_dpll_pin *pin;
1902 /* Check if the pin registrable to this DPLL */
1906 pin = zl3073x_dpll_pin_alloc(zldpll, dir, id);
1907 if (IS_ERR(pin)) {
1908 rc = PTR_ERR(pin);
1912 rc = zl3073x_dpll_pin_register(pin, index);
1916 list_add(&pin->list, &zldpll->pins);
1993 * zl3073x_dpll_pin_phase_offset_check - check for pin phase offset change
1994 * @pin: pin to check
1996 * Check for the change of DPLL to connected pin phase offset change.
2001 zl3073x_dpll_pin_phase_offset_check(struct zl3073x_dpll_pin *pin)
2003 struct zl3073x_dpll *zldpll = pin->dpll;
2010 ref = zl3073x_input_pin_ref_get(pin->id);
2012 /* Select register to read phase offset value depending on pin and
2014 * 1) For connected pin use dpll_phase_err_data register
2017 * report signal errors for given input pin
2019 if (pin->pin_state == DPLL_PIN_STATE_CONNECTED) {
2030 pin->label, ERR_PTR(rc));
2040 /* The pin is not connected or phase monitor disabled */
2057 if (phase_offset != pin->phase_offset) {
2059 pin->label, pin->phase_offset, phase_offset);
2060 pin->phase_offset = phase_offset;
2069 * zl3073x_dpll_pin_ffo_check - check for pin fractional frequency offset change
2070 * @pin: pin to check
2072 * Check for the given pin's fractional frequency change.
2077 zl3073x_dpll_pin_ffo_check(struct zl3073x_dpll_pin *pin)
2079 struct zl3073x_dpll *zldpll = pin->dpll;
2086 ref = zl3073x_input_pin_ref_get(pin->id);
2090 pin->label, ERR_PTR(rc));
2103 if (pin->freq_offset != ffo) {
2105 pin->label, pin->freq_offset, ffo);
2106 pin->freq_offset = ffo;
2129 struct zl3073x_dpll_pin *pin;
2149 /* Input pin monitoring does make sense only in automatic
2169 list_for_each_entry(pin, &zldpll->pins, list) {
2176 if (!zl3073x_dpll_is_input_pin(pin))
2179 rc = zl3073x_dpll_ref_state_get(pin, &state);
2183 pin->label, zldpll->id, ERR_PTR(rc));
2187 if (state != pin->pin_state) {
2188 dev_dbg(dev, "%s state changed: %u->%u\n", pin->label,
2189 pin->pin_state, state);
2190 pin->pin_state = state;
2196 if (zl3073x_dpll_pin_phase_offset_check(pin))
2199 if (zl3073x_dpll_pin_ffo_check(pin))
2204 dpll_pin_change_ntf(pin->dpll_pin);