drivers/dpll/dpll_netlink.c

51 static bool dpll_pin_available(struct dpll_pin *pin)
56 	if (!xa_get_mark(&dpll_pin_xa, pin->id, DPLL_REGISTERED))
58 	xa_for_each(&pin->parent_refs, i, par_ref)
59 		if (xa_get_mark(&dpll_pin_xa, par_ref->pin->id,
62 	xa_for_each(&pin->dpll_refs, i, par_ref)
70  * dpll_msg_add_pin_handle - attach pin handle attribute to a given message
71  * @msg: pointer to sk_buff message to attach a pin handle
72  * @pin: pin pointer
76  * * -EMSGSIZE - no space in message to attach pin handle
78 static int dpll_msg_add_pin_handle(struct sk_buff *msg, struct dpll_pin *pin)
80 	if (!pin)
82 	if (nla_put_u32(msg, DPLL_A_PIN_ID, pin->id))
93  * dpll_netdev_pin_handle_size - get size of pin handle attribute of a netdev
94  * @dev: netdev from which to get the pin
96  * Return: byte size of pin handle attribute, or 0 if @dev has no pin.
232 dpll_msg_add_pin_prio(struct sk_buff *msg, struct dpll_pin *pin,
243 	ret = ops->prio_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,
254 dpll_msg_add_pin_on_dpll_state(struct sk_buff *msg, struct dpll_pin *pin,
265 	ret = ops->state_on_dpll_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
276 dpll_msg_add_pin_direction(struct sk_buff *msg, struct dpll_pin *pin,
285 	ret = ops->direction_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,
296 dpll_msg_add_pin_phase_adjust(struct sk_buff *msg, struct dpll_pin *pin,
307 	ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
319 dpll_msg_add_phase_offset(struct sk_buff *msg, struct dpll_pin *pin,
330 	ret = ops->phase_offset_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
342 static int dpll_msg_add_ffo(struct sk_buff *msg, struct dpll_pin *pin,
353 	ret = ops->ffo_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
364 dpll_msg_add_pin_freq(struct sk_buff *msg, struct dpll_pin *pin,
375 	ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,
382 	for (fs = 0; fs < pin->prop.freq_supported_num; fs++) {
386 		freq = pin->prop.freq_supported[fs].min;
392 		freq = pin->prop.freq_supported[fs].max;
405 dpll_msg_add_pin_esync(struct sk_buff *msg, struct dpll_pin *pin,
416 	ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,
450 dpll_msg_add_pin_ref_sync(struct sk_buff *msg, struct dpll_pin *pin,
463 	pin_priv = dpll_pin_on_dpll_priv(dpll, pin);
464 	xa_for_each(&pin->ref_sync_pins, index, ref_sync_pin) {
470 		ret = ops->ref_sync_get(pin, pin_priv, ref_sync_pin,
490 static bool dpll_pin_is_freq_supported(struct dpll_pin *pin, u32 freq)
494 	for (fs = 0; fs < pin->prop.freq_supported_num; fs++)
495 		if (freq >= pin->prop.freq_supported[fs].min &&
496 		    freq <= pin->prop.freq_supported[fs].max)
502 dpll_msg_add_pin_parents(struct sk_buff *msg, struct dpll_pin *pin,
513 	xa_for_each(&pin->parent_refs, index, ref) {
517 		ppin = ref->pin;
519 		ret = ops->state_on_pin_get(pin,
520 					    dpll_pin_on_pin_priv(ppin, pin),
545 dpll_msg_add_pin_dplls(struct sk_buff *msg, struct dpll_pin *pin,
553 	xa_for_each(&pin->dpll_refs, index, ref) {
560 		ret = dpll_msg_add_pin_on_dpll_state(msg, pin, ref, extack);
563 		ret = dpll_msg_add_pin_prio(msg, pin, ref, extack);
566 		ret = dpll_msg_add_pin_direction(msg, pin, ref, extack);
569 		ret = dpll_msg_add_phase_offset(msg, pin, ref, extack);
583 dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,
586 	const struct dpll_pin_properties *prop = &pin->prop;
590 	ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);
593 	ret = dpll_msg_add_pin_handle(msg, pin);
597 			   module_name(pin->module)))
599 	if (nla_put_64bit(msg, DPLL_A_PIN_CLOCK_ID, sizeof(pin->clock_id),
600 			  &pin->clock_id, DPLL_A_PIN_PAD))
616 	ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
625 	ret = dpll_msg_add_pin_phase_adjust(msg, pin, ref, extack);
628 	ret = dpll_msg_add_ffo(msg, pin, ref, extack);
631 	ret = dpll_msg_add_pin_esync(msg, pin, ref, extack);
634 	if (!xa_empty(&pin->ref_sync_pins))
635 		ret = dpll_msg_add_pin_ref_sync(msg, pin, ref, extack);
638 	if (xa_empty(&pin->parent_refs))
639 		ret = dpll_msg_add_pin_dplls(msg, pin, extack);
641 		ret = dpll_msg_add_pin_parents(msg, pin, ref, extack);
751 dpll_pin_event_send(enum dpll_cmd event, struct dpll_pin *pin)
757 	if (!dpll_pin_available(pin))
767 	ret = dpll_cmd_pin_get_one(msg, pin, NULL);
783 int dpll_pin_create_ntf(struct dpll_pin *pin)
785 	return dpll_pin_event_send(DPLL_CMD_PIN_CREATE_NTF, pin);
788 int dpll_pin_delete_ntf(struct dpll_pin *pin)
790 	return dpll_pin_event_send(DPLL_CMD_PIN_DELETE_NTF, pin);
793 int __dpll_pin_change_ntf(struct dpll_pin *pin)
795 	return dpll_pin_event_send(DPLL_CMD_PIN_CHANGE_NTF, pin);
799  * dpll_pin_change_ntf - notify that the pin has been changed
800  * @pin: registered pin pointer
805 int dpll_pin_change_ntf(struct dpll_pin *pin)
810 	ret = __dpll_pin_change_ntf(pin);
843 dpll_pin_freq_set(struct dpll_pin *pin, struct nlattr *a,
853 	if (!dpll_pin_is_freq_supported(pin, freq)) {
858 	xa_for_each(&pin->dpll_refs, i, ref) {
865 	ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);
868 	ret = ops->frequency_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,
877 	xa_for_each(&pin->dpll_refs, i, ref) {
880 		ret = ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin),
889 	__dpll_pin_change_ntf(pin);
894 	xa_for_each(&pin->dpll_refs, i, ref) {
899 		if (ops->frequency_set(pin, dpll_pin_on_dpll_priv(dpll, pin),
907 dpll_pin_esync_set(struct dpll_pin *pin, struct nlattr *a,
919 	xa_for_each(&pin->dpll_refs, i, ref) {
927 	ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);
930 	ret = ops->esync_get(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,
947 	xa_for_each(&pin->dpll_refs, i, ref) {
952 		pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin);
953 		ret = ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll),
963 	__dpll_pin_change_ntf(pin);
968 	xa_for_each(&pin->dpll_refs, i, ref) {
975 		pin_dpll_priv = dpll_pin_on_dpll_priv(dpll, pin);
976 		if (ops->esync_set(pin, pin_dpll_priv, dpll, dpll_priv(dpll),
984 dpll_pin_ref_sync_state_set(struct dpll_pin *pin,
998 	ref_sync_pin = xa_find(&pin->ref_sync_pins, &ref_sync_pin_idx,
1001 		NL_SET_ERR_MSG(extack, "reference sync pin not found");
1005 		NL_SET_ERR_MSG(extack, "reference sync pin not available");
1008 	ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);
1012 		NL_SET_ERR_MSG(extack, "reference sync not supported by this pin");
1016 	ret = ops->ref_sync_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
1026 	xa_for_each(&pin->dpll_refs, i, ref) {
1029 		ret = ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin),
1041 	__dpll_pin_change_ntf(pin);
1046 	xa_for_each(&pin->dpll_refs, i, ref) {
1051 		if (ops->ref_sync_set(pin, dpll_pin_on_dpll_priv(dpll, pin),
1061 dpll_pin_ref_sync_set(struct dpll_pin *pin, struct nlattr *nest,
1071 		NL_SET_ERR_MSG(extack, "sync pin id expected");
1077 		NL_SET_ERR_MSG(extack, "sync pin state expected");
1082 	return dpll_pin_ref_sync_state_set(pin, sync_pin_id, state, extack);
1086 dpll_pin_on_pin_state_set(struct dpll_pin *pin, u32 parent_idx,
1099 	      pin->prop.capabilities)) {
1106 	parent_ref = xa_load(&pin->parent_refs, parent->pin_idx);
1113 		pin_priv = dpll_pin_on_pin_priv(parent, pin);
1115 		ret = ops->state_on_pin_set(pin, pin_priv, parent, parent_priv,
1120 	__dpll_pin_change_ntf(pin);
1126 dpll_pin_state_set(struct dpll_device *dpll, struct dpll_pin *pin,
1135 	      pin->prop.capabilities)) {
1139 	ref = xa_load(&pin->dpll_refs, dpll->id);
1144 	ret = ops->state_on_dpll_set(pin, dpll_pin_on_dpll_priv(dpll, pin),
1148 	__dpll_pin_change_ntf(pin);
1154 dpll_pin_prio_set(struct dpll_device *dpll, struct dpll_pin *pin,
1162 	      pin->prop.capabilities)) {
1166 	ref = xa_load(&pin->dpll_refs, dpll->id);
1171 	ret = ops->prio_set(pin, dpll_pin_on_dpll_priv(dpll, pin), dpll,
1175 	__dpll_pin_change_ntf(pin);
1181 dpll_pin_direction_set(struct dpll_pin *pin, struct dpll_device *dpll,
1190 	      pin->prop.capabilities)) {
1194 	ref = xa_load(&pin->dpll_refs, dpll->id);
1199 	ret = ops->direction_set(pin, dpll_pin_on_dpll_priv(dpll, pin),
1203 	__dpll_pin_change_ntf(pin);
1209 dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
1220 	if (phase_adj > pin->prop.phase_range.max ||
1221 	    phase_adj < pin->prop.phase_range.min) {
1227 	xa_for_each(&pin->dpll_refs, i, ref) {
1234 	ref = dpll_xa_ref_dpll_first(&pin->dpll_refs);
1237 	ret = ops->phase_adjust_get(pin, dpll_pin_on_dpll_priv(dpll, pin),
1247 	xa_for_each(&pin->dpll_refs, i, ref) {
1250 		ret = ops->phase_adjust_set(pin,
1251 					    dpll_pin_on_dpll_priv(dpll, pin),
1262 	__dpll_pin_change_ntf(pin);
1267 	xa_for_each(&pin->dpll_refs, i, ref) {
1272 		if (ops->phase_adjust_set(pin, dpll_pin_on_dpll_priv(dpll, pin),
1281 dpll_pin_parent_device_set(struct dpll_pin *pin, struct nlattr *parent_nest,
1304 	ref = xa_load(&pin->dpll_refs, dpll->id);
1306 		NL_SET_ERR_MSG(extack, "pin not connected to given parent device");
1311 		ret = dpll_pin_state_set(dpll, pin, state, extack);
1317 		ret = dpll_pin_prio_set(dpll, pin, prio, extack);
1323 		ret = dpll_pin_direction_set(pin, dpll, direction, extack);
1331 dpll_pin_parent_pin_set(struct dpll_pin *pin, struct nlattr *parent_nest,
1349 		ret = dpll_pin_on_pin_state_set(pin, ppin_idx, state, extack);
1358 dpll_pin_set_from_nlattr(struct dpll_pin *pin, struct genl_info *info)
1367 			ret = dpll_pin_freq_set(pin, a, info->extack);
1372 			ret = dpll_pin_phase_adj_set(pin, a, info->extack);
1377 			ret = dpll_pin_parent_device_set(pin, a, info->extack);
1382 			ret = dpll_pin_parent_pin_set(pin, a, info->extack);
1387 			ret = dpll_pin_esync_set(pin, a, info->extack);
1392 			ret = dpll_pin_ref_sync_set(pin, a, info->extack);
1409 	struct dpll_pin *pin_match = NULL, *pin;
1414 	xa_for_each_marked(&dpll_pin_xa, i, pin, DPLL_REGISTERED) {
1415 		prop = &pin->prop;
1416 		cid_match = clock_id ? pin->clock_id == clock_id : true;
1417 		mod_match = mod_name_attr && module_name(pin->module) ?
1419 				    module_name(pin->module)) : true;
1436 			pin_match = pin;
1506 	struct dpll_pin *pin;
1520 	pin = dpll_pin_find_from_nlattr(info);
1521 	if (!IS_ERR(pin)) {
1522 		if (!dpll_pin_available(pin)) {
1526 		ret = dpll_msg_add_pin_handle(msg, pin);
1539 	struct dpll_pin *pin = info->user_ptr[0];
1544 	if (!pin)
1555 	ret = dpll_cmd_pin_get_one(msg, pin, info->extack);
1568 	struct dpll_pin *pin;
1574 	xa_for_each_marked_start(&dpll_pin_xa, i, pin, DPLL_REGISTERED,
1576 		if (!dpll_pin_available(pin))
1586 		ret = dpll_cmd_pin_get_one(skb, pin, cb->extack);
1604 	struct dpll_pin *pin = info->user_ptr[0];
1606 	return dpll_pin_set_from_nlattr(pin, info);
1850 		NL_SET_ERR_MSG(info->extack, "pin not found");