Lines Matching refs:chan
25 #define ZYNQMP_DMA_ISR (chan->irq_offset + 0x100)
26 #define ZYNQMP_DMA_IMR (chan->irq_offset + 0x104)
27 #define ZYNQMP_DMA_IER (chan->irq_offset + 0x108)
28 #define ZYNQMP_DMA_IDS (chan->irq_offset + 0x10c)
141 #define ZYNQMP_DMA_DESC_SIZE(chan) (chan->desc_size)
143 #define to_chan(chan) container_of(chan, struct zynqmp_dma_chan, \
249 * @chan: Driver specific DMA channel
256 struct zynqmp_dma_chan *chan;
269 static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg,
272 lo_hi_writeq(value, chan->regs + reg);
277 * @chan: ZynqMP DMA DMA channel pointer
280 static void zynqmp_dma_update_desc_to_ctrlr(struct zynqmp_dma_chan *chan,
286 zynqmp_dma_writeq(chan, ZYNQMP_DMA_SRC_START_LSB, addr);
288 zynqmp_dma_writeq(chan, ZYNQMP_DMA_DST_START_LSB, addr);
293 * @chan: ZynqMP DMA channel pointer
296 static void zynqmp_dma_desc_config_eod(struct zynqmp_dma_chan *chan,
308 * @chan: ZynqMP DMA channel pointer
315 static void zynqmp_dma_config_sg_ll_desc(struct zynqmp_dma_chan *chan,
327 if (chan->is_dmacoherent) {
333 dma_addr_t addr = chan->desc_pool_p +
334 ((uintptr_t)sdesc - (uintptr_t)chan->desc_pool_v);
337 ddesc->nxtdscraddr = addr + ZYNQMP_DMA_DESC_SIZE(chan);
343 * @chan: ZynqMP DMA channel pointer
345 static void zynqmp_dma_init(struct zynqmp_dma_chan *chan)
349 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
350 val = readl(chan->regs + ZYNQMP_DMA_ISR);
351 writel(val, chan->regs + ZYNQMP_DMA_ISR);
353 if (chan->is_dmacoherent) {
357 writel(val, chan->regs + ZYNQMP_DMA_DSCR_ATTR);
360 val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
361 if (chan->is_dmacoherent) {
367 writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
370 val = readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
371 val = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
373 chan->idle = true;
384 struct zynqmp_dma_chan *chan = to_chan(tx->chan);
390 spin_lock_irqsave(&chan->lock, irqflags);
393 if (!list_empty(&chan->pending_list)) {
394 desc = list_last_entry(&chan->pending_list,
405 list_add_tail(&new->node, &chan->pending_list);
406 spin_unlock_irqrestore(&chan->lock, irqflags);
413 * @chan: ZynqMP DMA channel pointer
418 zynqmp_dma_get_descriptor(struct zynqmp_dma_chan *chan)
423 spin_lock_irqsave(&chan->lock, irqflags);
424 desc = list_first_entry(&chan->free_list,
427 spin_unlock_irqrestore(&chan->lock, irqflags);
431 memset((void *)desc->src_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
432 memset((void *)desc->dst_v, 0, ZYNQMP_DMA_DESC_SIZE(chan));
439 * @chan: ZynqMP DMA channel pointer
442 static void zynqmp_dma_free_descriptor(struct zynqmp_dma_chan *chan,
447 chan->desc_free_cnt++;
448 list_move_tail(&sdesc->node, &chan->free_list);
450 chan->desc_free_cnt++;
451 list_move_tail(&child->node, &chan->free_list);
457 * @chan: ZynqMP DMA channel pointer
460 static void zynqmp_dma_free_desc_list(struct zynqmp_dma_chan *chan,
466 zynqmp_dma_free_descriptor(chan, desc);
477 struct zynqmp_dma_chan *chan = to_chan(dchan);
481 ret = pm_runtime_resume_and_get(chan->dev);
485 chan->sw_desc_pool = kcalloc(ZYNQMP_DMA_NUM_DESCS, sizeof(*desc),
487 if (!chan->sw_desc_pool)
490 chan->idle = true;
491 chan->desc_free_cnt = ZYNQMP_DMA_NUM_DESCS;
493 INIT_LIST_HEAD(&chan->free_list);
496 desc = chan->sw_desc_pool + i;
497 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
499 list_add_tail(&desc->node, &chan->free_list);
502 chan->desc_pool_v = dma_alloc_coherent(chan->dev,
503 (2 * ZYNQMP_DMA_DESC_SIZE(chan) *
505 &chan->desc_pool_p, GFP_KERNEL);
506 if (!chan->desc_pool_v)
510 desc = chan->sw_desc_pool + i;
511 desc->src_v = (struct zynqmp_dma_desc_ll *) (chan->desc_pool_v +
512 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2));
514 desc->src_p = chan->desc_pool_p +
515 (i * ZYNQMP_DMA_DESC_SIZE(chan) * 2);
516 desc->dst_p = desc->src_p + ZYNQMP_DMA_DESC_SIZE(chan);
524 * @chan: ZynqMP DMA channel pointer
526 static void zynqmp_dma_start(struct zynqmp_dma_chan *chan)
528 writel(ZYNQMP_DMA_INT_EN_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IER);
529 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
530 chan->idle = false;
531 writel(ZYNQMP_DMA_ENABLE, chan->regs + ZYNQMP_DMA_CTRL2);
536 * @chan: ZynqMP DMA channel pointer
539 static void zynqmp_dma_handle_ovfl_int(struct zynqmp_dma_chan *chan, u32 status)
542 writel(0, chan->regs + ZYNQMP_DMA_TOTAL_BYTE);
544 readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
546 readl(chan->regs + ZYNQMP_DMA_IRQ_SRC_ACCT);
549 static void zynqmp_dma_config(struct zynqmp_dma_chan *chan)
553 val = readl(chan->regs + ZYNQMP_DMA_CTRL0);
555 writel(val, chan->regs + ZYNQMP_DMA_CTRL0);
557 val = readl(chan->regs + ZYNQMP_DMA_DATA_ATTR);
558 burst_val = __ilog2_u32(chan->src_burst_len);
561 burst_val = __ilog2_u32(chan->dst_burst_len);
564 writel(val, chan->regs + ZYNQMP_DMA_DATA_ATTR);
577 struct zynqmp_dma_chan *chan = to_chan(dchan);
579 chan->src_burst_len = clamp(config->src_maxburst, 1U,
581 chan->dst_burst_len = clamp(config->dst_maxburst, 1U,
589 * @chan: ZynqMP DMA channel pointer
591 static void zynqmp_dma_start_transfer(struct zynqmp_dma_chan *chan)
595 if (!chan->idle)
598 zynqmp_dma_config(chan);
600 desc = list_first_entry_or_null(&chan->pending_list,
605 list_splice_tail_init(&chan->pending_list, &chan->active_list);
606 zynqmp_dma_update_desc_to_ctrlr(chan, desc);
607 zynqmp_dma_start(chan);
613 * @chan: ZynqMP DMA channel
615 static void zynqmp_dma_chan_desc_cleanup(struct zynqmp_dma_chan *chan)
620 spin_lock_irqsave(&chan->lock, irqflags);
622 list_for_each_entry_safe(desc, next, &chan->done_list, node) {
627 spin_unlock_irqrestore(&chan->lock, irqflags);
629 spin_lock_irqsave(&chan->lock, irqflags);
633 zynqmp_dma_free_descriptor(chan, desc);
636 spin_unlock_irqrestore(&chan->lock, irqflags);
641 * @chan: ZynqMP DMA channel pointer
643 static void zynqmp_dma_complete_descriptor(struct zynqmp_dma_chan *chan)
647 desc = list_first_entry_or_null(&chan->active_list,
653 list_add_tail(&desc->node, &chan->done_list);
662 struct zynqmp_dma_chan *chan = to_chan(dchan);
665 spin_lock_irqsave(&chan->lock, irqflags);
666 zynqmp_dma_start_transfer(chan);
667 spin_unlock_irqrestore(&chan->lock, irqflags);
672 * @chan: ZynqMP DMA channel pointer
674 static void zynqmp_dma_free_descriptors(struct zynqmp_dma_chan *chan)
678 spin_lock_irqsave(&chan->lock, irqflags);
679 zynqmp_dma_free_desc_list(chan, &chan->active_list);
680 zynqmp_dma_free_desc_list(chan, &chan->pending_list);
681 zynqmp_dma_free_desc_list(chan, &chan->done_list);
682 spin_unlock_irqrestore(&chan->lock, irqflags);
691 struct zynqmp_dma_chan *chan = to_chan(dchan);
693 zynqmp_dma_free_descriptors(chan);
694 dma_free_coherent(chan->dev,
695 (2 * ZYNQMP_DMA_DESC_SIZE(chan) * ZYNQMP_DMA_NUM_DESCS),
696 chan->desc_pool_v, chan->desc_pool_p);
697 kfree(chan->sw_desc_pool);
698 pm_runtime_mark_last_busy(chan->dev);
699 pm_runtime_put_autosuspend(chan->dev);
704 * @chan: ZynqMP DMA channel pointer
706 static void zynqmp_dma_reset(struct zynqmp_dma_chan *chan)
710 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
712 spin_lock_irqsave(&chan->lock, irqflags);
713 zynqmp_dma_complete_descriptor(chan);
714 spin_unlock_irqrestore(&chan->lock, irqflags);
715 zynqmp_dma_chan_desc_cleanup(chan);
716 zynqmp_dma_free_descriptors(chan);
718 zynqmp_dma_init(chan);
730 struct zynqmp_dma_chan *chan = (struct zynqmp_dma_chan *)data;
734 isr = readl(chan->regs + ZYNQMP_DMA_ISR);
735 imr = readl(chan->regs + ZYNQMP_DMA_IMR);
738 writel(isr, chan->regs + ZYNQMP_DMA_ISR);
740 tasklet_schedule(&chan->tasklet);
745 chan->idle = true;
748 chan->err = true;
749 tasklet_schedule(&chan->tasklet);
750 dev_err(chan->dev, "Channel %p has errors\n", chan);
755 zynqmp_dma_handle_ovfl_int(chan, status);
756 dev_dbg(chan->dev, "Channel %p overflow interrupt\n", chan);
769 struct zynqmp_dma_chan *chan = from_tasklet(chan, t, tasklet);
773 if (chan->err) {
774 zynqmp_dma_reset(chan);
775 chan->err = false;
779 spin_lock_irqsave(&chan->lock, irqflags);
780 count = readl(chan->regs + ZYNQMP_DMA_IRQ_DST_ACCT);
782 zynqmp_dma_complete_descriptor(chan);
785 spin_unlock_irqrestore(&chan->lock, irqflags);
787 zynqmp_dma_chan_desc_cleanup(chan);
789 if (chan->idle) {
790 spin_lock_irqsave(&chan->lock, irqflags);
791 zynqmp_dma_start_transfer(chan);
792 spin_unlock_irqrestore(&chan->lock, irqflags);
804 struct zynqmp_dma_chan *chan = to_chan(dchan);
806 writel(ZYNQMP_DMA_IDS_DEFAULT_MASK, chan->regs + ZYNQMP_DMA_IDS);
807 zynqmp_dma_free_descriptors(chan);
818 struct zynqmp_dma_chan *chan = to_chan(dchan);
820 tasklet_kill(&chan->tasklet);
837 struct zynqmp_dma_chan *chan;
844 chan = to_chan(dchan);
848 spin_lock_irqsave(&chan->lock, irqflags);
849 if (desc_cnt > chan->desc_free_cnt) {
850 spin_unlock_irqrestore(&chan->lock, irqflags);
851 dev_dbg(chan->dev, "chan %p descs are not available\n", chan);
854 chan->desc_free_cnt = chan->desc_free_cnt - desc_cnt;
855 spin_unlock_irqrestore(&chan->lock, irqflags);
859 new = zynqmp_dma_get_descriptor(chan);
863 zynqmp_dma_config_sg_ll_desc(chan, desc, dma_src,
875 zynqmp_dma_desc_config_eod(chan, desc);
883 * @chan: ZynqMP DMA channel pointer
885 static void zynqmp_dma_chan_remove(struct zynqmp_dma_chan *chan)
887 if (!chan)
890 if (chan->irq)
891 devm_free_irq(chan->zdev->dev, chan->irq, chan);
892 tasklet_kill(&chan->tasklet);
893 list_del(&chan->common.device_node);
906 struct zynqmp_dma_chan *chan;
911 chan = devm_kzalloc(zdev->dev, sizeof(*chan), GFP_KERNEL);
912 if (!chan)
914 chan->dev = zdev->dev;
915 chan->zdev = zdev;
917 chan->regs = devm_platform_ioremap_resource(pdev, 0);
918 if (IS_ERR(chan->regs))
919 return PTR_ERR(chan->regs);
921 chan->bus_width = ZYNQMP_DMA_BUS_WIDTH_64;
922 chan->dst_burst_len = ZYNQMP_DMA_MAX_DST_BURST_LEN;
923 chan->src_burst_len = ZYNQMP_DMA_MAX_SRC_BURST_LEN;
924 err = of_property_read_u32(node, "xlnx,bus-width", &chan->bus_width);
930 if (chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_64 &&
931 chan->bus_width != ZYNQMP_DMA_BUS_WIDTH_128) {
938 chan->irq_offset = match_data->offset;
940 chan->is_dmacoherent = of_property_read_bool(node, "dma-coherent");
941 zdev->chan = chan;
942 tasklet_setup(&chan->tasklet, zynqmp_dma_do_tasklet);
943 spin_lock_init(&chan->lock);
944 INIT_LIST_HEAD(&chan->active_list);
945 INIT_LIST_HEAD(&chan->pending_list);
946 INIT_LIST_HEAD(&chan->done_list);
947 INIT_LIST_HEAD(&chan->free_list);
949 dma_cookie_init(&chan->common);
950 chan->common.device = &zdev->common;
951 list_add_tail(&chan->common.device_node, &zdev->common.channels);
953 zynqmp_dma_init(chan);
954 chan->irq = platform_get_irq(pdev, 0);
955 if (chan->irq < 0)
957 err = devm_request_irq(&pdev->dev, chan->irq, zynqmp_dma_irq_handler, 0,
958 "zynqmp-dma", chan);
962 chan->desc_size = sizeof(struct zynqmp_dma_desc_ll);
963 chan->idle = true;
979 return dma_get_slave_channel(&zdev->chan->common);
1131 p->dst_addr_widths = BIT(zdev->chan->bus_width / 8);
1132 p->src_addr_widths = BIT(zdev->chan->bus_width / 8);
1154 zynqmp_dma_chan_remove(zdev->chan);
1175 zynqmp_dma_chan_remove(zdev->chan);