Lines Matching refs:cdata

201 	const struct tegra_adma_chip_data *cdata;
209 	writel(val, tdma->base_addr + tdma->cdata->global_reg_offset + reg);
214 	return readl(tdma->base_addr + tdma->cdata->global_reg_offset + reg);
219 	writel(val, tdma->ch_base_addr + tdma->cdata->global_reg_offset + reg);
306 	tdma_ch_global_write(tdma, tdma->cdata->global_int_clear, 0x1);
317 				 tdma->cdata->global_reg_offset +
323 	if (tdma->cdata->set_global_pg_config)
324 		tdma->cdata->set_global_pg_config(tdma);
341 	if (sreq_index > tdma->cdata->ch_req_max) {
458 	tdma_ch_write(tdc, ADMA_CH_TC - tdc->tdma->cdata->ch_tc_offset_diff, ch_regs->tc);
460 	tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR - tdc->tdma->cdata->ch_tc_offset_diff,
462 	tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR - tdc->tdma->cdata->ch_tc_offset_diff,
465 	if (!tdc->tdma->cdata->global_ch_fifo_base)
486 			tdc->tdma->cdata->ch_tc_offset_diff);
658 	const struct tegra_adma_chip_data *cdata = tdc->tdma->cdata;
671 						      cdata->ch_req_mask,
672 						      cdata->ch_req_tx_shift);
682 						      cdata->ch_req_mask,
683 						      cdata->ch_req_rx_shift);
692 	ch_regs->ctrl |= ADMA_CH_CTRL_DIR(adma_dir, cdata->ch_dir_mask,
693 			cdata->ch_dir_shift) |
694 			 ADMA_CH_CTRL_MODE_CONTINUOUS(cdata->ch_mode_shift) |
696 	ch_regs->config |= cdata->adma_get_burst_config(burst_size);
698 	if (cdata->global_ch_config_base)
699 		ch_regs->global_config |= cdata->ch_config;
701 		ch_regs->config |= cdata->ch_config;
714 	if (tdc->sreq_index > cdata->sreq_index_offset)
716 			ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask,
720 			ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask,
856 		ch_reg->tc = tdma_ch_read(tdc, ADMA_CH_TC - tdma->cdata->ch_tc_offset_diff);
858 						tdma->cdata->ch_tc_offset_diff);
860 						tdma->cdata->ch_tc_offset_diff);
866 		if (!tdc->tdma->cdata->global_ch_fifo_base)
895 		if (tdma->cdata->set_global_pg_config)
896 			tdma->cdata->set_global_pg_config(tdma);
911 		tdma_ch_write(tdc, ADMA_CH_TC - tdma->cdata->ch_tc_offset_diff, ch_reg->tc);
912 		tdma_ch_write(tdc, ADMA_CH_LOWER_SRC_ADDR - tdma->cdata->ch_tc_offset_diff,
914 		tdma_ch_write(tdc, ADMA_CH_LOWER_TRG_ADDR - tdma->cdata->ch_tc_offset_diff,
918 		if (!tdc->tdma->cdata->global_ch_fifo_base)
1018 	const struct tegra_adma_chip_data *cdata;
1023 	cdata = of_device_get_match_data(&pdev->dev);
1024 	if (!cdata) {
1030 			    struct_size(tdma, channels, cdata->nr_channels),
1036 	tdma->cdata = cdata;
1037 	tdma->nr_channels = cdata->nr_channels;
1054 			ch_base_offset = cdata->ch_base_offset;
1078 		tdma->ch_base_addr = tdma->base_addr + cdata->ch_base_offset;
1112 		tdc->chan_addr = tdma->ch_base_addr + (cdata->ch_reg_size * i);
1115 			if (cdata->global_ch_fifo_base)
1116 				tdc->global_ch_fifo_offset = cdata->global_ch_fifo_base + (4 * i);
1118 			if (cdata->global_ch_config_base)
1120 					cdata->global_ch_config_base + (4 * i);