dma/stm32/stm32-dma3.c

246 	u32 ctr2;
381 		dev_dbg(chan2dev(chan), "| C%dTR2: %08x\n", chan->id, hwdesc->ctr2);
496 					u32 ctr1, u32 ctr2, bool is_last, bool is_cyclic)
504 	hwdesc->ctr2 = ctr2;
563 				   u32 *ccr, u32 *ctr1, u32 *ctr2,
756 	*ctr2 = _ctr2;
786 	writel_relaxed(hwdesc->ctr2, ddata->base + STM32_DMA3_CTR2(id));
1203 	u32 count, i, ctr1, ctr2;
1227 		ret = stm32_dma3_chan_prep_hw(chan, DMA_MEM_TO_MEM, &swdesc->ccr, &ctr1, &ctr2,
1233 					    ctr1, ctr2, next_size == remaining, false);
1262 	u32 i, j, count, ctr1, ctr2;
1294 				ret = stm32_dma3_chan_prep_hw(chan, dir, &swdesc->ccr, &ctr1, &ctr2,
1303 				ret = stm32_dma3_chan_prep_hw(chan, dir, &swdesc->ccr, &ctr1, &ctr2,
1314 						    ctr1, ctr2, j == (count - 1), false);
1350 	u32 count, i, ctr1, ctr2;
1372 		ret = stm32_dma3_chan_prep_hw(chan, DMA_MEM_TO_DEV, &swdesc->ccr, &ctr1, &ctr2,
1378 		ret = stm32_dma3_chan_prep_hw(chan, DMA_DEV_TO_MEM, &swdesc->ccr, &ctr1, &ctr2,
1398 					    ctr1, ctr2, i == (count - 1), true);