drivers/dma/ste_dma40.c

472  * @dma_cfg: The client configuration of this dma channel.
474  * @configured: whether the dma_cfg configuration is valid
499 	struct stedma40_chan_cfg	 dma_cfg;
881 			chan->dma_cfg.dir == DMA_DEV_TO_MEM))
1264 	u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
1267 	if ((d40c->dma_cfg.dir == DMA_DEV_TO_MEM) ||
1268 	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
1272 	if (d40c->dma_cfg.dir !=  DMA_DEV_TO_MEM)
1366 		return phy_map[d40c->dma_cfg.mode_opt];
1368 		return log_map[d40c->dma_cfg.mode_opt];
1420 	return num_elt * d40c->dma_cfg.dst_info.data_width;
1856 	int dev_type = d40c->dma_cfg.dev_type;
1865 	bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1870 	if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
1873 	} else if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
1874 		   d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1885 		if (d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
1887 			if (d40c->dma_cfg.use_fixed_channel) {
1888 				i = d40c->dma_cfg.phy_channel;
1926 		if (d40c->dma_cfg.use_fixed_channel) {
1927 			i = d40c->dma_cfg.phy_channel;
1986 		d40c->dma_cfg = dma40_memcpy_conf_log;
1987 		d40c->dma_cfg.dev_type = dma40_memcpy_channels[d40c->chan.chan_id];
1989 		d40_log_cfg(&d40c->dma_cfg,
1994 		d40c->dma_cfg = dma40_memcpy_conf_phy;
2015 	u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2033 	if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2034 	    d40c->dma_cfg.dir == DMA_MEM_TO_MEM)
2036 	else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2078 	u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dev_type);
2096 	if (d40c->dma_cfg.dir == DMA_MEM_TO_DEV ||
2097 	    d40c->dma_cfg.dir == DMA_MEM_TO_MEM) {
2099 	} else if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM) {
2137 	struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2165 	struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
2204 	cfg = &chan->dma_cfg;
2304 			d40c->dma_cfg = *info;
2316 	bool realtime = d40c->dma_cfg.realtime;
2317 	bool highprio = d40c->dma_cfg.high_priority;
2352 	if ((d40c->dma_cfg.dir ==  DMA_DEV_TO_MEM) ||
2353 	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2354 		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, true);
2356 	if ((d40c->dma_cfg.dir ==  DMA_MEM_TO_DEV) ||
2357 	    (d40c->dma_cfg.dir == DMA_DEV_TO_DEV))
2358 		__d40_set_prio_rt(d40c, d40c->dma_cfg.dev_type, false);
2442 		if (d40c->dma_cfg.dir == DMA_DEV_TO_MEM)
2444 				d40c->dma_cfg.dev_type * D40_LCPA_CHAN_SIZE;
2447 				d40c->dma_cfg.dev_type *
2458 		 d40c->dma_cfg.use_fixed_channel ? ", fixed" : "");
2682 	struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;