dma/qcom/gpi.c

528 	struct gpi_tre tre[MAX_TRE];
919 	void *tre = ch_ring->base + (ch_ring->el_size * imed_event->tre_index);
948 		gpi_tre = tre;
960 	 * we need to update ring rp to tre + 1
962 	tre += ch_ring->el_size;
963 	if (tre >= (ch_ring->base + ch_ring->len))
964 		tre = ch_ring->base;
965 	ch_ring->rp = tre;
1438 /* copy tre into transfer ring */
1445 	/* get next tre location we can copy */
1452 	/* copy the tre info */
1487 	/* reset the channels (clears any pending tre) */
1628 	struct gpi_tre *tre;
1631 	/* first create config tre if applicable */
1633 		tre = &desc->tre[tre_idx];
1636 		tre->dword[0] = u32_encode_bits(i2c->low_count, TRE_I2C_C0_TLOW);
1637 		tre->dword[0] |= u32_encode_bits(i2c->high_count, TRE_I2C_C0_THIGH);
1638 		tre->dword[0] |= u32_encode_bits(i2c->cycle_count, TRE_I2C_C0_TCYL);
1639 		tre->dword[0] |= u32_encode_bits(i2c->pack_enable, TRE_I2C_C0_TX_PACK);
1640 		tre->dword[0] |= u32_encode_bits(i2c->pack_enable, TRE_I2C_C0_RX_PACK);
1642 		tre->dword[1] = 0;
1644 		tre->dword[2] = u32_encode_bits(i2c->clk_div, TRE_C0_CLK_DIV);
1646 		tre->dword[3] = u32_encode_bits(TRE_TYPE_CONFIG0, TRE_FLAGS_TYPE);
1647 		tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN);
1650 	/* create the GO tre for Tx */
1652 		tre = &desc->tre[tre_idx];
1656 			tre->dword[0] = u32_encode_bits(I2C_READ, TRE_I2C_GO_CMD);
1658 			tre->dword[0] = u32_encode_bits(i2c->op, TRE_I2C_GO_CMD);
1660 		tre->dword[0] |= u32_encode_bits(i2c->addr, TRE_I2C_GO_ADDR);
1661 		tre->dword[0] |= u32_encode_bits(i2c->stretch, TRE_I2C_GO_STRETCH);
1663 		tre->dword[1] = 0;
1664 		tre->dword[2] = u32_encode_bits(i2c->rx_len, TRE_RX_LEN);
1666 		tre->dword[3] = u32_encode_bits(TRE_TYPE_GO, TRE_FLAGS_TYPE);
1669 			tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK);
1671 			tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN);
1676 		tre = &desc->tre[tre_idx];
1680 		tre->dword[0] = lower_32_bits(address);
1681 		tre->dword[1] = upper_32_bits(address);
1683 		tre->dword[2] = u32_encode_bits(sg_dma_len(sgl), TRE_DMA_LEN);
1685 		tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE);
1686 		tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOT);
1690 		dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0],
1691 			desc->tre[i].dword[1], desc->tre[i].dword[2], desc->tre[i].dword[3]);
1703 	struct gpi_tre *tre;
1707 	/* first create config tre if applicable */
1709 		tre = &desc->tre[tre_idx];
1712 		tre->dword[0] = u32_encode_bits(spi->word_len, TRE_SPI_C0_WORD_SZ);
1713 		tre->dword[0] |= u32_encode_bits(spi->loopback_en, TRE_SPI_C0_LOOPBACK);
1714 		tre->dword[0] |= u32_encode_bits(spi->clock_pol_high, TRE_SPI_C0_CPOL);
1715 		tre->dword[0] |= u32_encode_bits(spi->data_pol_high, TRE_SPI_C0_CPHA);
1716 		tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_TX_PACK);
1717 		tre->dword[0] |= u32_encode_bits(spi->pack_en, TRE_SPI_C0_RX_PACK);
1719 		tre->dword[1] = 0;
1721 		tre->dword[2] = u32_encode_bits(spi->clk_div, TRE_C0_CLK_DIV);
1722 		tre->dword[2] |= u32_encode_bits(spi->clk_src, TRE_C0_CLK_SRC);
1724 		tre->dword[3] = u32_encode_bits(TRE_TYPE_CONFIG0, TRE_FLAGS_TYPE);
1725 		tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN);
1728 	/* create the GO tre for Tx */
1730 		tre = &desc->tre[tre_idx];
1733 		tre->dword[0] = u32_encode_bits(spi->fragmentation, TRE_SPI_GO_FRAG);
1734 		tre->dword[0] |= u32_encode_bits(spi->cs, TRE_SPI_GO_CS);
1735 		tre->dword[0] |= u32_encode_bits(spi->cmd, TRE_SPI_GO_CMD);
1737 		tre->dword[1] = 0;
1739 		tre->dword[2] = u32_encode_bits(spi->rx_len, TRE_RX_LEN);
1741 		tre->dword[3] = u32_encode_bits(TRE_TYPE_GO, TRE_FLAGS_TYPE);
1743 			tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_IEOB);
1744 			tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK);
1746 			tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN);
1748 			tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_CHAIN);
1749 			tre->dword[3] |= u32_encode_bits(1, TRE_FLAGS_LINK);
1753 	/* create the dma tre */
1754 	tre = &desc->tre[tre_idx];
1761 	if (direction == DMA_MEM_TO_DEV && len <= 2 * sizeof(tre->dword[0])) {
1766 		tre->dword[0] = 0;
1767 		tre->dword[1] = 0;
1768 		memcpy(&tre->dword[0], sg_virt(sgl), len);
1770 		tre->dword[2] = u32_encode_bits(len, TRE_DMA_IMMEDIATE_LEN);
1771 		tre->dword[3] = u32_encode_bits(TRE_TYPE_IMMEDIATE_DMA, TRE_FLAGS_TYPE);
1773 		tre->dword[0] = lower_32_bits(address);
1774 		tre->dword[1] = upper_32_bits(address);
1776 		tre->dword[2] = u32_encode_bits(len, TRE_DMA_LEN);
1777 		tre->dword[3] = u32_encode_bits(TRE_TYPE_DMA, TRE_FLAGS_TYPE);
1780 	tre->dword[3] |= u32_encode_bits(direction == DMA_MEM_TO_DEV,
1784 		dev_dbg(dev, "TRE:%d %x:%x:%x:%x\n", i, desc->tre[i].dword[0],
1785 			desc->tre[i].dword[1], desc->tre[i].dword[2], desc->tre[i].dword[3]);
1790 /* copy tre into transfer ring */
1862 	void *tre, *wp = NULL;
1882 		tre = &gpi_desc->tre[i];
1883 		gpi_queue_xfer(gpii, gchan, tre, &wp);