Lines Matching refs:fsl_qdma
316 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
357 fsl_qdma->desc_allocated--;
487 struct fsl_qdma_engine *fsl_qdma)
494 queue_num = fsl_qdma->n_queues;
495 block_number = fsl_qdma->block_number;
528 queue_temp->block_base = fsl_qdma->block_base +
529 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
586 static int fsl_qdma_halt(struct fsl_qdma_engine *fsl_qdma)
590 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
593 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
595 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
596 for (j = 0; j < fsl_qdma->block_number; j++) {
597 block = fsl_qdma->block_base +
598 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
600 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BCQMR(i));
603 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DSR);
611 for (j = 0; j < fsl_qdma->block_number; j++) {
612 block = fsl_qdma->block_base +
613 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
616 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BSQMR);
622 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
630 fsl_qdma_queue_transfer_complete(struct fsl_qdma_engine *fsl_qdma,
640 struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
641 struct fsl_qdma_queue *fsl_status = fsl_qdma->status[id];
647 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQSR);
659 id * fsl_qdma->n_queues;
683 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
690 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
698 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
704 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
726 dev_err(fsl_qdma->dma_dev.dev,
744 struct fsl_qdma_engine *fsl_qdma = dev_id;
745 void __iomem *status = fsl_qdma->status_base;
751 intr = qdma_readl(fsl_qdma, status + FSL_QDMA_DEDR);
754 decfdw0r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW0R);
755 decfdw1r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW1R);
756 decfdw2r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW2R);
757 decfdw3r = qdma_readl(fsl_qdma, status + FSL_QDMA_DECFDW3R);
758 dev_err(fsl_qdma->dma_dev.dev,
763 qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
771 struct fsl_qdma_engine *fsl_qdma = dev_id;
772 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
774 id = irq - fsl_qdma->irq_base;
775 if (id < 0 && id > fsl_qdma->block_number) {
776 dev_err(fsl_qdma->dma_dev.dev,
778 irq, fsl_qdma->irq_base);
781 block = fsl_qdma->block_base +
782 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, id);
784 intr = qdma_readl(fsl_qdma, block + FSL_QDMA_BCQIDR(0));
787 intr = fsl_qdma_queue_transfer_complete(fsl_qdma, block, id);
790 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
792 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
793 qdma_writel(fsl_qdma, 0, block + FSL_QDMA_BCQIER(0));
794 dev_err(fsl_qdma->dma_dev.dev, "QDMA: status err!\n");
798 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
806 struct fsl_qdma_engine *fsl_qdma)
813 fsl_qdma->error_irq =
815 if (fsl_qdma->error_irq < 0)
816 return fsl_qdma->error_irq;
818 ret = devm_request_irq(&pdev->dev, fsl_qdma->error_irq,
820 "qDMA error", fsl_qdma);
826 for (i = 0; i < fsl_qdma->block_number; i++) {
828 fsl_qdma->queue_irq[i] =
831 if (fsl_qdma->queue_irq[i] < 0)
832 return fsl_qdma->queue_irq[i];
835 fsl_qdma->queue_irq[i],
839 fsl_qdma);
847 ret = irq_set_affinity_hint(fsl_qdma->queue_irq[i],
853 fsl_qdma->queue_irq[i]);
862 struct fsl_qdma_engine *fsl_qdma)
866 devm_free_irq(&pdev->dev, fsl_qdma->error_irq, fsl_qdma);
867 for (i = 0; i < fsl_qdma->block_number; i++)
868 devm_free_irq(&pdev->dev, fsl_qdma->queue_irq[i], fsl_qdma);
871 static int fsl_qdma_reg_init(struct fsl_qdma_engine *fsl_qdma)
876 void __iomem *status = fsl_qdma->status_base;
877 void __iomem *block, *ctrl = fsl_qdma->ctrl_base;
878 struct fsl_qdma_queue *fsl_queue = fsl_qdma->queue;
881 ret = fsl_qdma_halt(fsl_qdma);
883 dev_err(fsl_qdma->dma_dev.dev, "DMA halt failed!");
887 for (i = 0; i < fsl_qdma->block_number; i++) {
893 block = fsl_qdma->block_base +
894 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, i);
895 qdma_writel(fsl_qdma, FSL_QDMA_BCQIDR_CLEAR,
899 for (j = 0; j < fsl_qdma->block_number; j++) {
900 block = fsl_qdma->block_base +
901 FSL_QDMA_BLOCK_BASE_OFFSET(fsl_qdma, j);
902 for (i = 0; i < fsl_qdma->n_queues; i++) {
903 temp = fsl_queue + i + (j * fsl_qdma->n_queues);
912 qdma_writel(fsl_qdma, temp->bus_addr,
914 qdma_writel(fsl_qdma, temp->bus_addr,
921 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BCQMR(i));
930 qdma_writel(fsl_qdma, FSL_QDMA_SQCCMR_ENTER_WM,
940 qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
942 qdma_writel(fsl_qdma, fsl_qdma->status[j]->bus_addr,
945 qdma_writel(fsl_qdma, FSL_QDMA_BCQIER_CQTIE,
947 qdma_writel(fsl_qdma, FSL_QDMA_BSQICR_ICEN |
950 qdma_writel(fsl_qdma, FSL_QDMA_CQIER_MEIE |
957 (fsl_qdma->status[j]->n_cq) - 6);
959 qdma_writel(fsl_qdma, reg, block + FSL_QDMA_BSQMR);
960 reg = qdma_readl(fsl_qdma, block + FSL_QDMA_BSQMR);
964 qdma_writel(fsl_qdma, FSL_QDMA_DEDR_CLEAR, status + FSL_QDMA_DEDR);
965 qdma_writel(fsl_qdma, FSL_QDMA_DEIER_CLEAR, status + FSL_QDMA_DEIER);
967 reg = qdma_readl(fsl_qdma, ctrl + FSL_QDMA_DMR);
969 qdma_writel(fsl_qdma, reg, ctrl + FSL_QDMA_DMR);
1073 struct fsl_qdma_engine *fsl_qdma = fsl_chan->qdma;
1077 return fsl_qdma->desc_allocated;
1110 fsl_qdma->desc_allocated++;
1111 return fsl_qdma->desc_allocated;
1126 struct fsl_qdma_engine *fsl_qdma;
1149 len = sizeof(*fsl_qdma);
1150 fsl_qdma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1151 if (!fsl_qdma)
1155 fsl_qdma->chans = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1156 if (!fsl_qdma->chans)
1160 fsl_qdma->status = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1161 if (!fsl_qdma->status)
1165 fsl_qdma->queue_irq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
1166 if (!fsl_qdma->queue_irq)
1175 fsl_qdma->desc_allocated = 0;
1176 fsl_qdma->n_chans = chans;
1177 fsl_qdma->n_queues = queues;
1178 fsl_qdma->block_number = blk_num;
1179 fsl_qdma->block_offset = blk_off;
1181 mutex_init(&fsl_qdma->fsl_qdma_mutex);
1183 for (i = 0; i < fsl_qdma->block_number; i++) {
1184 fsl_qdma->status[i] = fsl_qdma_prep_status_queue(pdev);
1185 if (!fsl_qdma->status[i])
1188 fsl_qdma->ctrl_base = devm_platform_ioremap_resource(pdev, 0);
1189 if (IS_ERR(fsl_qdma->ctrl_base))
1190 return PTR_ERR(fsl_qdma->ctrl_base);
1192 fsl_qdma->status_base = devm_platform_ioremap_resource(pdev, 1);
1193 if (IS_ERR(fsl_qdma->status_base))
1194 return PTR_ERR(fsl_qdma->status_base);
1196 fsl_qdma->block_base = devm_platform_ioremap_resource(pdev, 2);
1197 if (IS_ERR(fsl_qdma->block_base))
1198 return PTR_ERR(fsl_qdma->block_base);
1199 fsl_qdma->queue = fsl_qdma_alloc_queue_resources(pdev, fsl_qdma);
1200 if (!fsl_qdma->queue)
1203 fsl_qdma->irq_base = platform_get_irq_byname(pdev, "qdma-queue0");
1204 if (fsl_qdma->irq_base < 0)
1205 return fsl_qdma->irq_base;
1207 fsl_qdma->feature = of_property_read_bool(np, "big-endian");
1208 INIT_LIST_HEAD(&fsl_qdma->dma_dev.channels);
1210 for (i = 0; i < fsl_qdma->n_chans; i++) {
1211 struct fsl_qdma_chan *fsl_chan = &fsl_qdma->chans[i];
1213 fsl_chan->qdma = fsl_qdma;
1214 fsl_chan->queue = fsl_qdma->queue + i % (fsl_qdma->n_queues *
1215 fsl_qdma->block_number);
1217 vchan_init(&fsl_chan->vchan, &fsl_qdma->dma_dev);
1220 dma_cap_set(DMA_MEMCPY, fsl_qdma->dma_dev.cap_mask);
1222 fsl_qdma->dma_dev.dev = &pdev->dev;
1223 fsl_qdma->dma_dev.device_free_chan_resources =
1225 fsl_qdma->dma_dev.device_alloc_chan_resources =
1227 fsl_qdma->dma_dev.device_tx_status = dma_cookie_status;
1228 fsl_qdma->dma_dev.device_prep_dma_memcpy = fsl_qdma_prep_memcpy;
1229 fsl_qdma->dma_dev.device_issue_pending = fsl_qdma_issue_pending;
1230 fsl_qdma->dma_dev.device_synchronize = fsl_qdma_synchronize;
1231 fsl_qdma->dma_dev.device_terminate_all = fsl_qdma_terminate_all;
1239 platform_set_drvdata(pdev, fsl_qdma);
1241 ret = fsl_qdma_reg_init(fsl_qdma);
1247 ret = fsl_qdma_irq_init(pdev, fsl_qdma);
1251 ret = dma_async_device_register(&fsl_qdma->dma_dev);
1274 struct fsl_qdma_engine *fsl_qdma = platform_get_drvdata(pdev);
1276 fsl_qdma_irq_exit(pdev, fsl_qdma);
1277 fsl_qdma_cleanup_vchan(&fsl_qdma->dma_dev);
1279 dma_async_device_unregister(&fsl_qdma->dma_dev);