qat/qat_common/qat_hal.c

304 	unsigned int reset_mask = handle->chip_info->icp_rst_mask;
305 	unsigned int reset_csr = handle->chip_info->icp_rst_csr;
423 	misc_ctl_csr = handle->chip_info->misc_ctl_csr;
475 	unsigned int clk_csr = handle->chip_info->glb_clk_enable_csr;
476 	unsigned int reset_mask = handle->chip_info->icp_rst_mask;
477 	unsigned int reset_csr = handle->chip_info->icp_rst_csr;
637 		if (handle->chip_info->nn)
702 		handle->chip_info->mmp_sram_size = 0;
703 		handle->chip_info->nn = false;
704 		handle->chip_info->lm2lm3 = true;
705 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG_2X;
706 		handle->chip_info->icp_rst_csr = ICP_RESET_CPP0;
708 			handle->chip_info->icp_rst_mask = 0x100155;
710 			handle->chip_info->icp_rst_mask = 0x100015;
711 		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE_CPP0;
712 		handle->chip_info->misc_ctl_csr = MISC_CONTROL_C4XXX;
713 		handle->chip_info->wakeup_event_val = 0x80000000;
714 		handle->chip_info->fw_auth = true;
715 		handle->chip_info->css_3k = true;
717 			handle->chip_info->dual_sign = true;
718 		handle->chip_info->tgroup_share_ustore = true;
719 		handle->chip_info->fcu_ctl_csr = FCU_CONTROL_4XXX;
720 		handle->chip_info->fcu_sts_csr = FCU_STATUS_4XXX;
721 		handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI_4XXX;
722 		handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO_4XXX;
723 		handle->chip_info->fcu_loaded_ae_csr = FCU_AE_LOADED_4XXX;
724 		handle->chip_info->fcu_loaded_ae_pos = 0;
735 		handle->chip_info->mmp_sram_size = 0;
736 		handle->chip_info->nn = true;
737 		handle->chip_info->lm2lm3 = false;
738 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
739 		handle->chip_info->icp_rst_csr = ICP_RESET;
740 		handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) |
742 		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
743 		handle->chip_info->misc_ctl_csr = MISC_CONTROL;
744 		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
745 		handle->chip_info->fw_auth = true;
746 		handle->chip_info->css_3k = false;
747 		handle->chip_info->tgroup_share_ustore = false;
748 		handle->chip_info->fcu_ctl_csr = FCU_CONTROL;
749 		handle->chip_info->fcu_sts_csr = FCU_STATUS;
750 		handle->chip_info->fcu_dram_addr_hi = FCU_DRAM_ADDR_HI;
751 		handle->chip_info->fcu_dram_addr_lo = FCU_DRAM_ADDR_LO;
752 		handle->chip_info->fcu_loaded_ae_csr = FCU_STATUS;
753 		handle->chip_info->fcu_loaded_ae_pos = FCU_LOADED_AE_POS;
762 		handle->chip_info->mmp_sram_size = 0x40000;
763 		handle->chip_info->nn = true;
764 		handle->chip_info->lm2lm3 = false;
765 		handle->chip_info->lm_size = ICP_QAT_UCLO_MAX_LMEM_REG;
766 		handle->chip_info->icp_rst_csr = ICP_RESET;
767 		handle->chip_info->icp_rst_mask = (hw_data->ae_mask << RST_CSR_AE_LSB) |
769 		handle->chip_info->glb_clk_enable_csr = ICP_GLOBAL_CLK_ENABLE;
770 		handle->chip_info->misc_ctl_csr = MISC_CONTROL;
771 		handle->chip_info->wakeup_event_val = WAKEUP_EVENT;
772 		handle->chip_info->fw_auth = false;
773 		handle->chip_info->css_3k = false;
774 		handle->chip_info->tgroup_share_ustore = false;
775 		handle->chip_info->fcu_ctl_csr = 0;
776 		handle->chip_info->fcu_sts_csr = 0;
777 		handle->chip_info->fcu_dram_addr_hi = 0;
778 		handle->chip_info->fcu_dram_addr_lo = 0;
779 		handle->chip_info->fcu_loaded_ae_csr = 0;
780 		handle->chip_info->fcu_loaded_ae_pos = 0;
793 	if (handle->chip_info->mmp_sram_size > 0) {
845 	handle->chip_info = kzalloc(sizeof(*handle->chip_info), GFP_KERNEL);
846 	if (!handle->chip_info) {
865 	if (!handle->chip_info->fw_auth) {
875 	kfree(handle->chip_info);
887 	kfree(handle->chip_info);
895 	u32 wakeup_val = handle->chip_info->wakeup_event_val;
902 	if (handle->chip_info->fw_auth) {
903 		fcu_ctl_csr = handle->chip_info->fcu_ctl_csr;
904 		fcu_sts_csr = handle->chip_info->fcu_sts_csr;
928 	if (!handle->chip_info->fw_auth)
1019 	if (handle->chip_info->lm2lm3) {
1090 	if (handle->chip_info->lm2lm3) {
1581 	if (!handle->chip_info->nn) {