Lines Matching +full:safexcel +full:- +full:eip197b
1 // SPDX-License-Identifier: GPL-2.0
5 * Antoine Tenart <antoine.tenart@free-electrons.com>
10 #include <linux/dma-mapping.h>
25 #include "safexcel.h"
45 writel(0, priv->base + EIP197_FLUE_IFC_LUT(i));
51 for (i = 0; i < priv->config.rings; i++) {
52 writel(0, priv->base + EIP197_FLUE_CACHEBASE_LO(i));
53 writel(0, priv->base + EIP197_FLUE_CACHEBASE_HI(i));
55 priv->base + EIP197_FLUE_CONFIG(i));
57 writel(0, priv->base + EIP197_FLUE_OFFSETS);
58 writel(0, priv->base + EIP197_FLUE_ARC4_OFFSET);
69 val = readl(priv->base + EIP197_CS_RAM_CTRL);
72 writel(val, priv->base + EIP197_CS_RAM_CTRL);
89 actbank = min(maxbanks - 1, 0);
90 while ((addrhi - addrlo) > stride) {
96 priv->base + EIP197_CLASSIFICATION_RAMS +
102 addralias = addrmid - delta;
105 priv->base + EIP197_CLASSIFICATION_RAMS +
112 val = readl(priv->base + EIP197_CLASSIFICATION_RAMS +
137 priv->base + offset);
139 val = EIP197_CS_RC_NEXT(i + 1) | EIP197_CS_RC_PREV(i - 1);
142 else if (i == cs_rc_max - 1)
144 writel(val, priv->base + offset + 4);
146 writel(0, priv->base + offset + 8);
147 writel(0, priv->base + offset + 12);
154 priv->base + EIP197_CLASSIFICATION_RAMS +
172 val = readl(priv->base + EIP197_CS_RAM_CTRL);
175 writel(val, priv->base + EIP197_CS_RAM_CTRL);
176 val = readl(priv->base + EIP197_CS_RAM_CTRL);
180 writel(0, priv->base + EIP197_TRC_ECCCTRL);
186 val = readl(priv->base + EIP197_TRC_PARAMS);
188 writel(val, priv->base + EIP197_TRC_PARAMS);
198 val = readl(priv->base + EIP197_TRC_PARAMS);
201 writel(val, priv->base + EIP197_TRC_PARAMS);
207 writel(0, priv->base + EIP197_TRC_ECCCTRL);
211 dev_err(priv->dev, "Record cache probing failed (%d,%d).",
213 return -ENODEV;
234 cs_ht_sz = __fls(asize - cs_rc_max) - 2;
238 cs_rc_max = min_t(uint, cs_rc_abs_max, asize - (cs_ht_wc >> 2));
244 val = readl(priv->base + EIP197_CS_RAM_CTRL);
246 writel(val, priv->base + EIP197_CS_RAM_CTRL);
250 EIP197_TRC_FREECHAIN_TAIL_PTR(cs_rc_max - 1);
251 writel(val, priv->base + EIP197_TRC_FREECHAIN);
256 writel(val, priv->base + EIP197_TRC_PARAMS2);
262 writel(val, priv->base + EIP197_TRC_PARAMS);
264 dev_info(priv->dev, "TRC init: %dd,%da (%dr,%dh)\n",
274 for (pe = 0; pe < priv->config.pes; pe++) {
309 if (priv->flags & EIP197_OCE)
323 for (i = 0; i < fw->size / sizeof(u32); i++) {
324 if (priv->data->fw_little_endian)
325 val = le32_to_cpu(((const __le32 *)fw->data)[i]);
327 val = be32_to_cpu(((const __be32 *)fw->data)[i]);
330 priv->base + EIP197_CLASSIFICATION_RAMS +
335 return i - EIP197_FW_TERMINAL_NOPS;
352 for (pe = 0; pe < priv->config.pes; pe++) {
358 pollcnt--;
361 dev_err(priv->dev, "FW(%d) for PE %d failed to start\n",
375 for (pe = 0; pe < priv->config.pes; pe++) {
383 val = EIP197_PE_ICE_UENG_START_OFFSET((ifppsz - 1) &
392 val = EIP197_PE_ICE_UENG_START_OFFSET((ipuesz - 1) &
419 if (priv->data->version == EIP197D_MRVL)
421 else if (priv->data->version == EIP197B_MRVL ||
422 priv->data->version == EIP197_DEVBRD)
423 dir = "eip197b";
424 else if (priv->data->version == EIP197C_MXL)
427 return -ENODEV;
431 snprintf(fw_path, 37, "inside-secure/%s/%s", dir, fw_name[i]);
432 ret = firmware_request_nowarn(&fw[i], fw_path, priv->dev);
434 if (minifw || priv->data->version != EIP197B_MRVL)
438 * EIP197b.
441 priv->dev);
452 for (pe = 0; pe < priv->config.pes; pe++)
459 dev_dbg(priv->dev, "Firmware loaded successfully\n");
463 ret = -ENODEV;
471 dev_dbg(priv->dev, "Firmware set not (fully) present or init failed, falling back to BCLA mode\n");
477 dev_err(priv->dev, "Firmware load failed.\n");
487 cd_size_rnd = (priv->config.cd_size +
488 (BIT(priv->hwconfig.hwdataw) - 1)) >>
489 priv->hwconfig.hwdataw;
491 if (priv->flags & SAFEXCEL_HW_EIP197) {
493 cd_fetch_cnt = (1 << priv->hwconfig.hwcfsize) / cd_size_rnd;
495 (priv->config.pes * EIP197_FETCH_DEPTH));
498 cd_fetch_cnt = ((1 << priv->hwconfig.hwcfsize) /
499 cd_size_rnd) - 1;
503 * we need to check whether we can fit even 1 for low-end EIP196's!
506 dev_err(priv->dev, "Unable to fit even 1 command desc!\n");
507 return -ENODEV;
510 for (i = 0; i < priv->config.rings; i++) {
512 writel(lower_32_bits(priv->ring[i].cdr.base_dma),
514 writel(upper_32_bits(priv->ring[i].cdr.base_dma),
518 (priv->config.cd_offset << 14) | priv->config.cd_size,
521 (cd_size_rnd << priv->hwconfig.hwdataw)) << 16) |
522 (cd_fetch_cnt * (priv->config.cd_offset / sizeof(u32))),
545 (BIT(priv->hwconfig.hwdataw) - 1)) >>
546 priv->hwconfig.hwdataw;
547 if (priv->flags & SAFEXCEL_HW_EIP197) {
549 rd_fetch_cnt = (1 << priv->hwconfig.hwrfsize) / rd_size_rnd;
551 (priv->config.pes * EIP197_FETCH_DEPTH));
554 rd_fetch_cnt = ((1 << priv->hwconfig.hwrfsize) /
555 rd_size_rnd) - 1;
558 for (i = 0; i < priv->config.rings; i++) {
560 writel(lower_32_bits(priv->ring[i].rdr.base_dma),
562 writel(upper_32_bits(priv->ring[i].rdr.base_dma),
565 writel(EIP197_xDR_DESC_MODE_64BIT | (priv->config.rd_offset << 14) |
566 priv->config.rd_size,
570 (rd_size_rnd << priv->hwconfig.hwdataw)) << 16) |
571 (rd_fetch_cnt * (priv->config.rd_offset / sizeof(u32))),
599 dev_dbg(priv->dev, "HW init: using %d pipe(s) and %d ring(s)\n",
600 priv->config.pes, priv->config.rings);
606 if (priv->flags & SAFEXCEL_HW_EIP197) {
626 for (pe = 0; pe < priv->config.pes; pe++) {
633 if (priv->flags & EIP197_PE_ARB)
659 if (priv->flags & SAFEXCEL_HW_EIP197)
662 GENMASK(priv->config.rings - 1, 0),
677 if (priv->hwconfig.hwnumpes > 4) {
692 if (priv->flags & SAFEXCEL_HW_EIP197)
720 for (i = 0; i < priv->config.rings; i++) {
741 writel((EIP197_DEFAULT_RING_SIZE * priv->config.cd_offset),
746 for (i = 0; i < priv->config.rings; i++) {
764 writel((EIP197_DEFAULT_RING_SIZE * priv->config.rd_offset),
768 for (pe = 0; pe < priv->config.pes; pe++) {
770 writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
774 writel(EIP197_DxE_THR_CTRL_EN | GENMASK(priv->config.rings - 1, 0),
781 if (priv->flags & EIP197_SIMPLE_TRC) {
785 priv->base + EIP197_STRC_CONFIG);
788 } else if (priv->flags & SAFEXCEL_HW_EIP197) {
794 if (priv->flags & EIP197_ICE) {
809 int coal = min_t(int, priv->ring[ring].requests, EIP197_MAX_BATCH_SZ);
829 req = priv->ring[ring].req;
830 backlog = priv->ring[ring].backlog;
835 spin_lock_bh(&priv->ring[ring].queue_lock);
836 backlog = crypto_get_backlog(&priv->ring[ring].queue);
837 req = crypto_dequeue_request(&priv->ring[ring].queue);
838 spin_unlock_bh(&priv->ring[ring].queue_lock);
841 priv->ring[ring].req = NULL;
842 priv->ring[ring].backlog = NULL;
847 ctx = crypto_tfm_ctx(req->tfm);
848 ret = ctx->send(req, ring, &commands, &results);
853 crypto_request_complete(backlog, -EINPROGRESS);
869 * the request and the backlog for the next dequeue call (per-ring).
871 priv->ring[ring].req = req;
872 priv->ring[ring].backlog = backlog;
878 spin_lock_bh(&priv->ring[ring].lock);
880 priv->ring[ring].requests += nreq;
882 if (!priv->ring[ring].busy) {
884 priv->ring[ring].busy = true;
887 spin_unlock_bh(&priv->ring[ring].lock);
890 writel((rdesc * priv->config.rd_offset),
894 writel((cdesc * priv->config.cd_offset),
902 struct result_data_desc *result_data = rdp + priv->config.res_offset;
904 if (likely((!rdesc->last_seg) || /* Rest only valid if last seg! */
905 ((!rdesc->descriptor_overflow) &&
906 (!rdesc->buffer_overflow) &&
907 (!result_data->error_code))))
910 if (rdesc->descriptor_overflow)
911 dev_err(priv->dev, "Descriptor overflow detected");
913 if (rdesc->buffer_overflow)
914 dev_err(priv->dev, "Buffer overflow detected");
916 if (result_data->error_code & 0x4066) {
918 dev_err(priv->dev,
920 result_data->error_code);
922 return -EIO;
923 } else if (result_data->error_code &
930 return -EINVAL;
931 } else if (result_data->error_code & BIT(9)) {
933 return -EBADMSG;
936 /* All other non-fatal errors */
937 return -EINVAL;
947 priv->ring[ring].rdr_req[i] = req;
955 return priv->ring[ring].rdr_req[i];
964 cdesc = safexcel_ring_next_rptr(priv, &priv->ring[ring].cdr);
966 dev_err(priv->dev,
970 } while (!cdesc->last_seg);
988 cdesc->control_data.type = EIP197_TYPE_EXTENDED;
989 cdesc->control_data.options = 0;
990 cdesc->control_data.context_lo &= ~EIP197_CONTEXT_SIZE_MASK;
991 cdesc->control_data.control0 = CONTEXT_CONTROL_INV_TR;
1006 safexcel_ring_rollback_wptr(priv, &priv->ring[ring].cdr);
1031 ctx = crypto_tfm_ctx(req->tfm);
1032 ndesc = ctx->handle_result(priv, ring, req,
1035 dev_err(priv->dev, "failed to handle result (%d)\n",
1053 (tot_descs * priv->config.rd_offset),
1063 spin_lock_bh(&priv->ring[ring].lock);
1065 priv->ring[ring].requests -= handled;
1068 if (!priv->ring[ring].requests)
1069 priv->ring[ring].busy = false;
1071 spin_unlock_bh(&priv->ring[ring].lock);
1079 safexcel_dequeue(data->priv, data->ring);
1090 struct safexcel_crypto_priv *priv = irq_data->priv;
1091 int ring = irq_data->ring, rc = IRQ_NONE;
1108 dev_err(priv->dev, "RDR: fatal error.\n");
1127 struct safexcel_crypto_priv *priv = irq_data->priv;
1128 int ring = irq_data->ring;
1132 queue_work(priv->ring[ring].workqueue,
1133 &priv->ring[ring].work_data.work);
1151 dev = &pci_pdev->dev;
1163 dev = &plf_pdev->dev;
1169 return -ENXIO;
1263 safexcel_algs[i]->priv = priv;
1266 if ((safexcel_algs[i]->algo_mask & priv->hwconfig.algo_flags) !=
1267 safexcel_algs[i]->algo_mask)
1271 if (safexcel_algs[i]->type == SAFEXCEL_ALG_TYPE_SKCIPHER)
1272 ret = crypto_register_skcipher(&safexcel_algs[i]->alg.skcipher);
1273 else if (safexcel_algs[i]->type == SAFEXCEL_ALG_TYPE_AEAD)
1274 ret = crypto_register_aead(&safexcel_algs[i]->alg.aead);
1276 ret = crypto_register_ahash(&safexcel_algs[i]->alg.ahash);
1287 if ((safexcel_algs[j]->algo_mask & priv->hwconfig.algo_flags) !=
1288 safexcel_algs[j]->algo_mask)
1292 if (safexcel_algs[j]->type == SAFEXCEL_ALG_TYPE_SKCIPHER)
1293 crypto_unregister_skcipher(&safexcel_algs[j]->alg.skcipher);
1294 else if (safexcel_algs[j]->type == SAFEXCEL_ALG_TYPE_AEAD)
1295 crypto_unregister_aead(&safexcel_algs[j]->alg.aead);
1297 crypto_unregister_ahash(&safexcel_algs[j]->alg.ahash);
1309 if ((safexcel_algs[i]->algo_mask & priv->hwconfig.algo_flags) !=
1310 safexcel_algs[i]->algo_mask)
1314 if (safexcel_algs[i]->type == SAFEXCEL_ALG_TYPE_SKCIPHER)
1315 crypto_unregister_skcipher(&safexcel_algs[i]->alg.skcipher);
1316 else if (safexcel_algs[i]->type == SAFEXCEL_ALG_TYPE_AEAD)
1317 crypto_unregister_aead(&safexcel_algs[i]->alg.aead);
1319 crypto_unregister_ahash(&safexcel_algs[i]->alg.ahash);
1325 u32 mask = BIT(priv->hwconfig.hwdataw) - 1;
1327 priv->config.pes = priv->hwconfig.hwnumpes;
1328 priv->config.rings = min_t(u32, priv->hwconfig.hwnumrings, max_rings);
1330 priv->config.rings = min_t(u32, priv->config.rings,
1331 priv->hwconfig.hwnumraic);
1333 priv->config.cd_size = EIP197_CD64_FETCH_SIZE;
1334 priv->config.cd_offset = (priv->config.cd_size + mask) & ~mask;
1335 priv->config.cdsh_offset = (EIP197_MAX_TOKENS + mask) & ~mask;
1338 priv->config.res_offset = (EIP197_RD64_FETCH_SIZE + mask) & ~mask;
1340 priv->config.rd_size = priv->config.res_offset +
1342 priv->config.rd_offset = (priv->config.rd_size + mask) & ~mask;
1345 priv->config.cd_offset *= sizeof(u32);
1346 priv->config.cdsh_offset *= sizeof(u32);
1347 priv->config.rd_offset *= sizeof(u32);
1348 priv->config.res_offset *= sizeof(u32);
1353 struct safexcel_register_offsets *offsets = &priv->offsets;
1355 if (priv->flags & SAFEXCEL_HW_EIP197) {
1356 offsets->hia_aic = EIP197_HIA_AIC_BASE;
1357 offsets->hia_aic_g = EIP197_HIA_AIC_G_BASE;
1358 offsets->hia_aic_r = EIP197_HIA_AIC_R_BASE;
1359 offsets->hia_aic_xdr = EIP197_HIA_AIC_xDR_BASE;
1360 offsets->hia_dfe = EIP197_HIA_DFE_BASE;
1361 offsets->hia_dfe_thr = EIP197_HIA_DFE_THR_BASE;
1362 offsets->hia_dse = EIP197_HIA_DSE_BASE;
1363 offsets->hia_dse_thr = EIP197_HIA_DSE_THR_BASE;
1364 offsets->hia_gen_cfg = EIP197_HIA_GEN_CFG_BASE;
1365 offsets->pe = EIP197_PE_BASE;
1366 offsets->global = EIP197_GLOBAL_BASE;
1368 offsets->hia_aic = EIP97_HIA_AIC_BASE;
1369 offsets->hia_aic_g = EIP97_HIA_AIC_G_BASE;
1370 offsets->hia_aic_r = EIP97_HIA_AIC_R_BASE;
1371 offsets->hia_aic_xdr = EIP97_HIA_AIC_xDR_BASE;
1372 offsets->hia_dfe = EIP97_HIA_DFE_BASE;
1373 offsets->hia_dfe_thr = EIP97_HIA_DFE_THR_BASE;
1374 offsets->hia_dse = EIP97_HIA_DSE_BASE;
1375 offsets->hia_dse_thr = EIP97_HIA_DSE_THR_BASE;
1376 offsets->hia_gen_cfg = EIP97_HIA_GEN_CFG_BASE;
1377 offsets->pe = EIP97_PE_BASE;
1378 offsets->global = EIP97_GLOBAL_BASE;
1393 struct device *dev = priv->dev;
1397 priv->context_pool = dmam_pool_create("safexcel-context", dev,
1400 if (!priv->context_pool)
1401 return -ENOMEM;
1408 version = readl(priv->base + EIP97_HIA_AIC_BASE + EIP197_HIA_VERSION);
1412 priv->hwconfig.hiaver = EIP197_VERSION_MASK(version);
1414 /* read back byte-swapped, so complement byte swap bits */
1416 priv->hwconfig.hiaver = EIP197_VERSION_SWAP(version);
1419 version = readl(priv->base + EIP197_HIA_AIC_BASE +
1422 priv->hwconfig.hiaver = EIP197_VERSION_MASK(version);
1423 priv->flags |= SAFEXCEL_HW_EIP197;
1426 /* read back byte-swapped, so complement swap bits */
1428 priv->hwconfig.hiaver = EIP197_VERSION_SWAP(version);
1429 priv->flags |= SAFEXCEL_HW_EIP197;
1431 return -ENODEV;
1439 * If the version was read byte-swapped, we need to flip the device
1441 * byte-swapped ...
1455 if (((priv->flags & SAFEXCEL_HW_EIP197) &&
1458 ((!(priv->flags & SAFEXCEL_HW_EIP197) &&
1464 dev_err(priv->dev, "Probing for EIP97/EIP19x failed - no such device (read %08x)\n",
1466 return -ENODEV;
1469 priv->hwconfig.hwver = EIP197_VERSION_MASK(version);
1476 dev_err(priv->dev, "EIP%d: EIP206 not detected\n", peid);
1477 return -ENODEV;
1479 priv->hwconfig.ppver = EIP197_VERSION_MASK(version);
1485 return -ENODEV;
1487 priv->hwconfig.pever = EIP197_VERSION_MASK(version);
1492 priv->hwconfig.icever = 0;
1493 priv->hwconfig.ocever = 0;
1494 priv->hwconfig.psever = 0;
1495 if (priv->flags & SAFEXCEL_HW_EIP197) {
1499 priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) &
1501 priv->hwconfig.hwcfsize = ((hiaopt >> EIP197_CFSIZE_OFFSET) &
1504 priv->hwconfig.hwrfsize = ((hiaopt >> EIP197_RFSIZE_OFFSET) &
1507 priv->hwconfig.hwnumpes = (hiaopt >> EIP197_N_PES_OFFSET) &
1509 priv->hwconfig.hwnumrings = (hiaopt >> EIP197_N_RINGS_OFFSET) &
1512 priv->flags |= EIP197_PE_ARB;
1514 priv->flags |= EIP197_ICE;
1521 return -ENODEV;
1523 priv->hwconfig.icever = EIP197_VERSION_MASK(version);
1526 priv->flags |= EIP197_OCE;
1531 return -ENODEV;
1533 priv->hwconfig.psever = EIP197_VERSION_MASK(version);
1540 return -ENODEV;
1542 priv->hwconfig.ocever = EIP197_VERSION_MASK(version);
1546 priv->flags |= EIP197_SIMPLE_TRC;
1548 priv->flags |= EIP197_TRC_CACHE;
1551 priv->hwconfig.hwdataw = (hiaopt >> EIP197_HWDATAW_OFFSET) &
1553 priv->hwconfig.hwcfsize = (hiaopt >> EIP97_CFSIZE_OFFSET) &
1555 priv->hwconfig.hwrfsize = (hiaopt >> EIP97_RFSIZE_OFFSET) &
1557 priv->hwconfig.hwnumpes = 1; /* by definition */
1558 priv->hwconfig.hwnumrings = (hiaopt >> EIP197_N_RINGS_OFFSET) &
1569 priv->hwconfig.hwnumraic = i;
1570 /* Low-end EIP196 may not have any ring AIC's ... */
1571 if (!priv->hwconfig.hwnumraic) {
1572 dev_err(priv->dev, "No ring interrupt controller present!\n");
1573 return -ENODEV;
1577 priv->hwconfig.algo_flags = readl(EIP197_PE(priv) +
1581 dev_info(priv->dev, "EIP%d:%x(%d,%d,%d,%d)-HIA:%x(%d,%d,%d),PE:%x/%x(alg:%08x)/%x/%x/%x\n",
1582 peid, priv->hwconfig.hwver, hwctg, priv->hwconfig.hwnumpes,
1583 priv->hwconfig.hwnumrings, priv->hwconfig.hwnumraic,
1584 priv->hwconfig.hiaver, priv->hwconfig.hwdataw,
1585 priv->hwconfig.hwcfsize, priv->hwconfig.hwrfsize,
1586 priv->hwconfig.ppver, priv->hwconfig.pever,
1587 priv->hwconfig.algo_flags, priv->hwconfig.icever,
1588 priv->hwconfig.ocever, priv->hwconfig.psever);
1592 if (IS_ENABLED(CONFIG_PCI) && priv->data->version == EIP197_DEVBRD) {
1594 * Request MSI vectors for global + 1 per ring -
1600 priv->config.rings + 1,
1601 priv->config.rings + 1,
1610 priv->ring = devm_kcalloc(dev, priv->config.rings,
1611 sizeof(*priv->ring),
1613 if (!priv->ring)
1614 return -ENOMEM;
1616 for (i = 0; i < priv->config.rings; i++) {
1622 &priv->ring[i].cdr,
1623 &priv->ring[i].rdr);
1629 priv->ring[i].rdr_req = devm_kcalloc(dev,
1631 sizeof(*priv->ring[i].rdr_req),
1633 if (!priv->ring[i].rdr_req) {
1634 ret = -ENOMEM;
1640 ret = -ENOMEM;
1644 ring_irq->priv = priv;
1645 ring_irq->ring = i;
1660 priv->ring[i].irq = irq;
1661 priv->ring[i].work_data.priv = priv;
1662 priv->ring[i].work_data.ring = i;
1663 INIT_WORK(&priv->ring[i].work_data.work,
1667 priv->ring[i].workqueue =
1669 if (!priv->ring[i].workqueue) {
1670 ret = -ENOMEM;
1674 priv->ring[i].requests = 0;
1675 priv->ring[i].busy = false;
1677 crypto_init_queue(&priv->ring[i].queue,
1680 spin_lock_init(&priv->ring[i].lock);
1681 spin_lock_init(&priv->ring[i].queue_lock);
1684 atomic_set(&priv->ring_used, 0);
1701 for (i = 0; i < priv->config.rings; i++) {
1702 if (priv->ring[i].irq)
1703 irq_set_affinity_hint(priv->ring[i].irq, NULL);
1704 if (priv->ring[i].workqueue)
1705 destroy_workqueue(priv->ring[i].workqueue);
1715 for (i = 0; i < priv->config.rings; i++) {
1734 struct device *dev = &pdev->dev;
1740 return -ENOMEM;
1742 priv->dev = dev;
1743 priv->data = (struct safexcel_priv_data *)of_device_get_match_data(dev);
1747 priv->base = devm_platform_ioremap_resource(pdev, 0);
1748 if (IS_ERR(priv->base)) {
1750 return PTR_ERR(priv->base);
1753 priv->clk = devm_clk_get(&pdev->dev, NULL);
1754 ret = PTR_ERR_OR_ZERO(priv->clk);
1756 if (ret != -ENOENT) {
1760 ret = clk_prepare_enable(priv->clk);
1767 priv->reg_clk = devm_clk_get(&pdev->dev, "reg");
1768 ret = PTR_ERR_OR_ZERO(priv->reg_clk);
1770 if (ret != -ENOENT) {
1774 ret = clk_prepare_enable(priv->reg_clk);
1793 clk_disable_unprepare(priv->reg_clk);
1795 clk_disable_unprepare(priv->clk);
1807 clk_disable_unprepare(priv->reg_clk);
1808 clk_disable_unprepare(priv->clk);
1810 for (i = 0; i < priv->config.rings; i++) {
1811 irq_set_affinity_hint(priv->ring[i].irq, NULL);
1812 destroy_workqueue(priv->ring[i].workqueue);
1839 .compatible = "inside-secure,safexcel-eip97ies",
1843 .compatible = "inside-secure,safexcel-eip197b",
1847 .compatible = "inside-secure,safexcel-eip197d",
1851 .compatible = "inside-secure,safexcel-eip197c-mxl",
1856 .compatible = "inside-secure,safexcel-eip97",
1860 .compatible = "inside-secure,safexcel-eip197",
1872 .name = "crypto-safexcel",
1877 /* PCIE devices - i.e. Inside Secure development boards */
1882 struct device *dev = &pdev->dev;
1889 ent->vendor, ent->device, ent->subvendor,
1890 ent->subdevice, ent->driver_data);
1894 return -ENOMEM;
1896 priv->dev = dev;
1897 priv->data = (struct safexcel_priv_data *)ent->driver_data;
1914 priv->base = pcim_iomap_table(pdev)[0];
1916 if (priv->data->version == EIP197_DEVBRD) {
1917 dev_dbg(dev, "Device identified as FPGA based development board - applying HW reset\n");
1947 return -ENODEV;
1952 writel(1, priv->base + EIP197_XLX_GPIO_BASE);
1955 writel(0, priv->base + EIP197_XLX_GPIO_BASE);
1974 for (i = 0; i < priv->config.rings; i++)
1975 destroy_workqueue(priv->ring[i].workqueue);
1992 .name = "crypto-safexcel",
2028 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
2031 MODULE_DESCRIPTION("Support for SafeXcel cryptographic engines: EIP97 & EIP197");
2037 MODULE_FIRMWARE("inside-secure/eip197b/ifpp.bin");
2038 MODULE_FIRMWARE("inside-secure/eip197b/ipue.bin");
2039 MODULE_FIRMWARE("inside-secure/eip197d/ifpp.bin");
2040 MODULE_FIRMWARE("inside-secure/eip197d/ipue.bin");
2041 MODULE_FIRMWARE("inside-secure/eip197_minifw/ifpp.bin");
2042 MODULE_FIRMWARE("inside-secure/eip197_minifw/ipue.bin");