Lines Matching defs:qm

55 static inline bool dae_is_support(struct hisi_qm *qm)
57 	if (test_bit(QM_SUPPORT_DAE, &qm->caps))
63 int hisi_dae_set_user_domain(struct hisi_qm *qm)
68 	if (!dae_is_support(qm))
71 	val = readl(qm->io_base + DAE_MEM_START_OFFSET);
73 	writel(val, qm->io_base + DAE_MEM_START_OFFSET);
74 	ret = readl_relaxed_poll_timeout(qm->io_base + DAE_MEM_DONE_OFFSET, val,
78 		pci_err(qm->pdev, "failed to init dae memory!\n");
83 int hisi_dae_set_alg(struct hisi_qm *qm)
87 	if (!dae_is_support(qm))
90 	if (!qm->uacce)
93 	len = strlen(qm->uacce->algs);
96 		pci_err(qm->pdev, "algorithm name is too long!\n");
101 		strcat((char *)qm->uacce->algs, "\n");
103 	strcat((char *)qm->uacce->algs, DAE_ALG_NAME);
108 static void hisi_dae_master_ooo_ctrl(struct hisi_qm *qm, bool enable)
112 	axi_val = readl(qm->io_base + DAE_AXI_CFG_OFFSET);
121 	writel(axi_val, qm->io_base + DAE_AXI_CFG_OFFSET);
122 	writel(err_val, qm->io_base + DAE_ERR_SHUTDOWN_OFFSET);
125 void hisi_dae_hw_error_enable(struct hisi_qm *qm)
127 	if (!dae_is_support(qm))
131 	writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_SOURCE_OFFSET);
134 	writel(DAE_ERR_CE_MASK, qm->io_base + DAE_ERR_CE_OFFSET);
135 	writel(DAE_ERR_NFE_MASK, qm->io_base + DAE_ERR_NFE_OFFSET);
136 	writel(DAE_ERR_FE_MASK, qm->io_base + DAE_ERR_FE_OFFSET);
138 	hisi_dae_master_ooo_ctrl(qm, true);
141 	writel(DAE_ERR_ENABLE_MASK, qm->io_base + DAE_ERR_ENABLE_OFFSET);
144 void hisi_dae_hw_error_disable(struct hisi_qm *qm)
146 	if (!dae_is_support(qm))
149 	writel(0, qm->io_base + DAE_ERR_ENABLE_OFFSET);
150 	hisi_dae_master_ooo_ctrl(qm, false);
153 static u32 hisi_dae_get_hw_err_status(struct hisi_qm *qm)
155 	return readl(qm->io_base + DAE_ERR_STATUS_OFFSET);
158 static void hisi_dae_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
160 	if (!dae_is_support(qm))
163 	writel(err_sts, qm->io_base + DAE_ERR_SOURCE_OFFSET);
166 static void hisi_dae_disable_error_report(struct hisi_qm *qm, u32 err_type)
168 	writel(DAE_ERR_NFE_MASK & (~err_type), qm->io_base + DAE_ERR_NFE_OFFSET);
171 static void hisi_dae_log_hw_error(struct hisi_qm *qm, u32 err_type)
174 	struct device *dev = &qm->pdev->dev;
187 			ecc_info = readl(qm->io_base + DAE_ECC_INFO_OFFSET);
193 enum acc_err_result hisi_dae_get_err_result(struct hisi_qm *qm)
197 	if (!dae_is_support(qm))
200 	err_status = hisi_dae_get_hw_err_status(qm);
204 	hisi_dae_log_hw_error(qm, err_status);
208 		hisi_dae_disable_error_report(qm, err_status);
211 	hisi_dae_clear_hw_err_status(qm, err_status);
216 bool hisi_dae_dev_is_abnormal(struct hisi_qm *qm)
220 	if (!dae_is_support(qm))
223 	err_status = hisi_dae_get_hw_err_status(qm);
230 int hisi_dae_close_axi_master_ooo(struct hisi_qm *qm)
235 	if (!dae_is_support(qm))
238 	val = readl(qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET);
240 	writel(val, qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET);
242 	ret = readl_relaxed_poll_timeout(qm->io_base + DAE_AM_RETURN_OFFSET,
246 		dev_err(&qm->pdev->dev, "failed to close dae axi ooo!\n");
251 void hisi_dae_open_axi_master_ooo(struct hisi_qm *qm)
255 	if (!dae_is_support(qm))
258 	val = readl(qm->io_base + DAE_AXI_CFG_OFFSET);
260 	writel(val & ~DAE_AXI_SHUTDOWN_EN_MASK, qm->io_base + DAE_AXI_CFG_OFFSET);
261 	writel(val | DAE_AXI_SHUTDOWN_EN_MASK, qm->io_base + DAE_AXI_CFG_OFFSET);