Lines Matching defs:qm

49 	int (*dump_fn)(struct hisi_qm *qm, char *cmd, char *info_name);
153 static void dump_show(struct hisi_qm *qm, void *info,
156 	struct device *dev = &qm->pdev->dev;
168 static int qm_sqc_dump(struct hisi_qm *qm, char *s, char *name)
170 	struct device *dev = &qm->pdev->dev;
179 	if (ret || qp_id >= qm->qp_num) {
180 		dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1);
184 	ret = qm_set_and_get_xqc(qm, QM_MB_CMD_SQC, &sqc, qp_id, 1);
188 		dump_show(qm, &sqc, sizeof(struct qm_sqc), name);
193 	down_read(&qm->qps_lock);
194 	if (qm->sqc) {
195 		memcpy(&sqc, qm->sqc + qp_id, sizeof(struct qm_sqc));
198 		dump_show(qm, &sqc, sizeof(struct qm_sqc), "SOFT SQC");
200 	up_read(&qm->qps_lock);
205 static int qm_cqc_dump(struct hisi_qm *qm, char *s, char *name)
207 	struct device *dev = &qm->pdev->dev;
216 	if (ret || qp_id >= qm->qp_num) {
217 		dev_err(dev, "Please input qp num (0-%u)", qm->qp_num - 1);
221 	ret = qm_set_and_get_xqc(qm, QM_MB_CMD_CQC, &cqc, qp_id, 1);
225 		dump_show(qm, &cqc, sizeof(struct qm_cqc), name);
230 	down_read(&qm->qps_lock);
231 	if (qm->cqc) {
232 		memcpy(&cqc, qm->cqc + qp_id, sizeof(struct qm_cqc));
235 		dump_show(qm, &cqc, sizeof(struct qm_cqc), "SOFT CQC");
237 	up_read(&qm->qps_lock);
242 static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, char *name)
244 	struct device *dev = &qm->pdev->dev;
267 	ret = qm_set_and_get_xqc(qm, cmd, xeqc, 0, 1);
275 	dump_show(qm, xeqc, size, name);
280 static int q_dump_param_parse(struct hisi_qm *qm, char *s,
283 	struct device *dev = &qm->pdev->dev;
284 	unsigned int qp_num = qm->qp_num;
320 static int qm_sq_dump(struct hisi_qm *qm, char *s, char *name)
322 	u16 sq_depth = qm->qp_array->sq_depth;
328 	ret = q_dump_param_parse(qm, s, &sqe_id, &qp_id, sq_depth);
332 	sqe = kzalloc(qm->sqe_size, GFP_KERNEL);
336 	qp = &qm->qp_array[qp_id];
337 	memcpy(sqe, qp->sqe + sqe_id * qm->sqe_size, qm->sqe_size);
338 	memset(sqe + qm->debug.sqe_mask_offset, QM_SQE_ADDR_MASK,
339 	       qm->debug.sqe_mask_len);
341 	dump_show(qm, sqe, qm->sqe_size, name);
348 static int qm_cq_dump(struct hisi_qm *qm, char *s, char *name)
355 	ret = q_dump_param_parse(qm, s, &cqe_id, &qp_id, qm->qp_array->cq_depth);
359 	qp = &qm->qp_array[qp_id];
361 	dump_show(qm, cqe_curr, sizeof(struct qm_cqe), name);
366 static int qm_eq_aeq_dump(struct hisi_qm *qm, char *s, char *name)
368 	struct device *dev = &qm->pdev->dev;
383 		xeq_depth = qm->eq_depth;
386 		xeq_depth = qm->aeq_depth;
395 	down_read(&qm->qps_lock);
397 	if (qm->eqe && !strcmp(name, "EQE")) {
398 		xeqe = qm->eqe + xeqe_id;
399 	} else if (qm->aeqe && !strcmp(name, "AEQE")) {
400 		xeqe = qm->aeqe + xeqe_id;
406 	dump_show(qm, xeqe, size, name);
409 	up_read(&qm->qps_lock);
413 static int qm_dbg_help(struct hisi_qm *qm, char *s)
415 	struct device *dev = &qm->pdev->dev;
471 static int qm_cmd_write_dump(struct hisi_qm *qm, const char *cmd_buf)
473 	struct device *dev = &qm->pdev->dev;
489 		ret = qm_dbg_help(qm, s);
496 			ret = qm_cmd_dump_table[i].dump_fn(qm, s,
516 	struct hisi_qm *qm = filp->private_data;
523 	ret = hisi_qm_get_dfx_access(qm);
528 	if (unlikely(atomic_read(&qm->status.flags) == QM_STOP)) {
550 	ret = qm_cmd_write_dump(qm, cmd_buf);
561 	hisi_qm_put_dfx_access(qm);
582 	struct hisi_qm *qm = pci_get_drvdata(pdev);
588 	ret = hisi_qm_get_dfx_access(qm);
597 	hisi_qm_put_dfx_access(qm);
603 	struct hisi_qm *qm = s->private;
606 	if (qm->fun_type == QM_HW_PF) {
614 	regset.base = qm->io_base;
615 	regset.dev = &qm->pdev->dev;
624 static u32 current_q_read(struct hisi_qm *qm)
626 	return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT;
629 static int current_q_write(struct hisi_qm *qm, u32 val)
633 	if (val >= qm->debug.curr_qm_qp_num)
637 	      (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_FUN_MASK);
638 	writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
641 	      (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_FUN_MASK);
642 	writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
647 static u32 clear_enable_read(struct hisi_qm *qm)
649 	return readl(qm->io_base + QM_DFX_CNT_CLR_CE);
653 static int clear_enable_write(struct hisi_qm *qm, u32 rd_clr_ctrl)
658 	writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE);
663 static u32 current_qm_read(struct hisi_qm *qm)
665 	return readl(qm->io_base + QM_DFX_MB_CNT_VF);
668 static int qm_get_vf_qp_num(struct hisi_qm *qm, u32 fun_num)
671 	u32 num_vfs = qm->vfs_num;
673 	vfq_num = (qm->ctrl_qp_num - qm->qp_num) / num_vfs;
674 	if (vfq_num >= qm->max_qp_num)
675 		return qm->max_qp_num;
677 	remain_q_num = (qm->ctrl_qp_num - qm->qp_num) % num_vfs;
678 	if (vfq_num + remain_q_num <= qm->max_qp_num)
688 static int current_qm_write(struct hisi_qm *qm, u32 val)
692 	if (val > qm->vfs_num)
697 		qm->debug.curr_qm_qp_num = qm->qp_num;
699 		qm->debug.curr_qm_qp_num = qm_get_vf_qp_num(qm, val);
701 	writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
702 	writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
705 	      (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
706 	writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
709 	      (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
710 	writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
720 	struct hisi_qm *qm = file_to_qm(file);
725 	ret = hisi_qm_get_dfx_access(qm);
732 		val = current_qm_read(qm);
735 		val = current_q_read(qm);
738 		val = clear_enable_read(qm);
745 	hisi_qm_put_dfx_access(qm);
751 	hisi_qm_put_dfx_access(qm);
760 	struct hisi_qm *qm = file_to_qm(file);
780 	ret = hisi_qm_get_dfx_access(qm);
787 		ret = current_qm_write(qm, val);
790 		ret = current_q_write(qm, val);
793 		ret = clear_enable_write(qm, val);
800 	hisi_qm_put_dfx_access(qm);
815 static void dfx_regs_uninit(struct hisi_qm *qm,
834 static struct dfx_diff_registers *dfx_regs_init(struct hisi_qm *qm,
859 			diff_regs[i].regs[j] = readl(qm->io_base + base_offset);
874 static int qm_diff_regs_init(struct hisi_qm *qm,
879 	qm->debug.qm_diff_regs = dfx_regs_init(qm, qm_diff_regs, ARRAY_SIZE(qm_diff_regs));
880 	if (IS_ERR(qm->debug.qm_diff_regs)) {
881 		ret = PTR_ERR(qm->debug.qm_diff_regs);
882 		qm->debug.qm_diff_regs = NULL;
886 	qm->debug.acc_diff_regs = dfx_regs_init(qm, dregs, reg_len);
887 	if (IS_ERR(qm->debug.acc_diff_regs)) {
888 		dfx_regs_uninit(qm, qm->debug.qm_diff_regs, ARRAY_SIZE(qm_diff_regs));
889 		ret = PTR_ERR(qm->debug.acc_diff_regs);
890 		qm->debug.acc_diff_regs = NULL;
897 static void qm_last_regs_uninit(struct hisi_qm *qm)
899 	struct qm_debug *debug = &qm->debug;
901 	if (qm->fun_type == QM_HW_VF || !debug->qm_last_words)
908 static int qm_last_regs_init(struct hisi_qm *qm)
911 	struct qm_debug *debug = &qm->debug;
914 	if (qm->fun_type == QM_HW_VF)
922 		debug->qm_last_words[i] = readl_relaxed(qm->io_base +
929 static void qm_diff_regs_uninit(struct hisi_qm *qm, u32 reg_len)
931 	dfx_regs_uninit(qm, qm->debug.acc_diff_regs, reg_len);
932 	qm->debug.acc_diff_regs = NULL;
933 	dfx_regs_uninit(qm, qm->debug.qm_diff_regs, ARRAY_SIZE(qm_diff_regs));
934 	qm->debug.qm_diff_regs = NULL;
939  * @qm: device qm handle.
943 int hisi_qm_regs_debugfs_init(struct hisi_qm *qm,
948 	if (!qm || !dregs)
951 	if (qm->fun_type != QM_HW_PF)
954 	ret = qm_last_regs_init(qm);
956 		dev_info(&qm->pdev->dev, "failed to init qm words memory!\n");
960 	ret = qm_diff_regs_init(qm, dregs, reg_len);
962 		qm_last_regs_uninit(qm);
972  * @qm: device qm handle.
975 void hisi_qm_regs_debugfs_uninit(struct hisi_qm *qm, u32 reg_len)
977 	if (!qm || qm->fun_type != QM_HW_PF)
980 	qm_diff_regs_uninit(qm, reg_len);
981 	qm_last_regs_uninit(qm);
987  * @qm: device qm handle.
992 void hisi_qm_acc_diff_regs_dump(struct hisi_qm *qm, struct seq_file *s,
998 	if (!qm || !s || !dregs)
1001 	ret = hisi_qm_get_dfx_access(qm);
1005 	down_read(&qm->qps_lock);
1012 			val = readl(qm->io_base + base_offset);
1018 	up_read(&qm->qps_lock);
1020 	hisi_qm_put_dfx_access(qm);
1024 void hisi_qm_show_last_dfx_regs(struct hisi_qm *qm)
1026 	struct qm_debug *debug = &qm->debug;
1027 	struct pci_dev *pdev = qm->pdev;
1031 	if (qm->fun_type == QM_HW_VF || !debug->qm_last_words)
1035 		val = readl_relaxed(qm->io_base + qm_dfx_regs[i].offset);
1044 	struct hisi_qm *qm = s->private;
1046 	hisi_qm_acc_diff_regs_dump(qm, s, qm->debug.qm_diff_regs,
1055 	struct hisi_qm *qm = s->private;
1060 	ret = hisi_qm_get_dfx_access(qm);
1062 		val = readl(qm->io_base + QM_IN_IDLE_ST_REG);
1063 		hisi_qm_put_dfx_access(qm);
1080 	struct hisi_qm *qm = filp->private_data;
1084 	val = atomic_read(&qm->status.flags);
1096 static void qm_create_debugfs_file(struct hisi_qm *qm, struct dentry *dir,
1099 	struct debugfs_file *file = qm->debug.files + index;
1103 	file->debug = &qm->debug;
1130  * hisi_qm_debug_init() - Initialize qm related debugfs files.
1131  * @qm: The qm for which we want to add debugfs files.
1133  * Create qm related debugfs files.
1135 void hisi_qm_debug_init(struct hisi_qm *qm)
1137 	struct dfx_diff_registers *qm_regs = qm->debug.qm_diff_regs;
1138 	struct qm_dev_dfx *dev_dfx = &qm->debug.dev_dfx;
1139 	struct qm_dfx *dfx = &qm->debug.dfx;
1144 	qm_d = debugfs_create_dir("qm", qm->debug.debug_root);
1145 	qm->debug.qm_d = qm_d;
1148 	if (qm->fun_type == QM_HW_PF) {
1149 		debugfs_create_file("qm_state", 0444, qm->debug.qm_d,
1150 					qm, &qm_state_fops);
1152 		qm_create_debugfs_file(qm, qm->debug.debug_root, CURRENT_QM);
1154 			qm_create_debugfs_file(qm, qm->debug.qm_d, i);
1158 		debugfs_create_file("diff_regs", 0444, qm->debug.qm_d,
1159 					qm, &qm_diff_regs_fops);
1161 	debugfs_create_file("regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops);
1163 	debugfs_create_file("cmd", 0600, qm->debug.qm_d, qm, &qm_cmd_fops);
1165 	debugfs_create_file("status", 0444, qm->debug.qm_d, qm,
1168 	debugfs_create_u32("dev_state", 0444, qm->debug.qm_d, &dev_dfx->dev_state);
1169 	debugfs_create_u32("dev_timeout", 0644, qm->debug.qm_d, &dev_dfx->dev_timeout);
1180 	if (test_bit(QM_SUPPORT_FUNC_QOS, &qm->caps))
1181 		hisi_qm_set_algqos_init(qm);
1186  * hisi_qm_debug_regs_clear() - clear qm debug related registers.
1187  * @qm: The qm for which we want to clear its debug registers.
1189 void hisi_qm_debug_regs_clear(struct hisi_qm *qm)
1195 	writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
1196 	writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
1199 	writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
1200 	writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
1206 	writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
1210 		readl(qm->io_base + regs->offset);
1215 	writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);