allwinner/sun4i-ss/sun4i-ss-core.c

1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
5  * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
24 #include "sun4i-ss.h"
50 				.cra_driver_name = "md5-sun4i-ss",
51 				.cra_priority = 300,
76 				.cra_driver_name = "sha1-sun4i-ss",
77 				.cra_priority = 300,
97 			.cra_driver_name = "cbc-aes-sun4i-ss",
98 			.cra_priority = 300,
118 			.cra_driver_name = "ecb-aes-sun4i-ss",
119 			.cra_priority = 300,
140 			.cra_driver_name = "cbc-des-sun4i-ss",
141 			.cra_priority = 300,
161 			.cra_driver_name = "ecb-des-sun4i-ss",
162 			.cra_priority = 300,
183 			.cra_driver_name = "cbc-des3-sun4i-ss",
184 			.cra_priority = 300,
204 			.cra_driver_name = "ecb-des3-sun4i-ss",
205 			.cra_priority = 300,
223 			.cra_priority		= 300,
276 	reset_control_assert(ss->reset);
278 	clk_disable_unprepare(ss->ssclk);
279 	clk_disable_unprepare(ss->busclk);
289 	err = clk_prepare_enable(ss->busclk);
291 		dev_err(ss->dev, "Cannot prepare_enable busclk\n");
295 	err = clk_prepare_enable(ss->ssclk);
297 		dev_err(ss->dev, "Cannot prepare_enable ssclk\n");
301 	err = reset_control_deassert(ss->reset);
303 		dev_err(ss->dev, "Cannot deassert reset control\n");
326 	pm_runtime_use_autosuspend(ss->dev);
327 	pm_runtime_set_autosuspend_delay(ss->dev, 2000);
329 	err = pm_runtime_set_suspended(ss->dev);
332 	pm_runtime_enable(ss->dev);
338 	pm_runtime_disable(ss->dev);
350 	if (!pdev->dev.of_node)
351 		return -ENODEV;
353 	ss = devm_kzalloc(&pdev->dev, sizeof(*ss), GFP_KERNEL);
355 		return -ENOMEM;
357 	ss->base = devm_platform_ioremap_resource(pdev, 0);
358 	if (IS_ERR(ss->base)) {
359 		dev_err(&pdev->dev, "Cannot request MMIO\n");
360 		return PTR_ERR(ss->base);
363 	ss->variant = of_device_get_match_data(&pdev->dev);
364 	if (!ss->variant) {
365 		dev_err(&pdev->dev, "Missing Security System variant\n");
366 		return -EINVAL;
369 	ss->ssclk = devm_clk_get(&pdev->dev, "mod");
370 	if (IS_ERR(ss->ssclk)) {
371 		err = PTR_ERR(ss->ssclk);
372 		dev_err(&pdev->dev, "Cannot get SS clock err=%d\n", err);
375 	dev_dbg(&pdev->dev, "clock ss acquired\n");
377 	ss->busclk = devm_clk_get(&pdev->dev, "ahb");
378 	if (IS_ERR(ss->busclk)) {
379 		err = PTR_ERR(ss->busclk);
380 		dev_err(&pdev->dev, "Cannot get AHB SS clock err=%d\n", err);
383 	dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
385 	ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
386 	if (IS_ERR(ss->reset))
387 		return PTR_ERR(ss->reset);
388 	if (!ss->reset)
389 		dev_info(&pdev->dev, "no reset control found\n");
395 	err = clk_set_rate(ss->ssclk, cr_mod);
397 		dev_err(&pdev->dev, "Cannot set clock rate to ssclk\n");
406 	cr = clk_get_rate(ss->busclk);
408 		dev_dbg(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
411 		dev_warn(&pdev->dev, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
414 	cr = clk_get_rate(ss->ssclk);
417 			dev_warn(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
420 			dev_dbg(&pdev->dev, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
423 		dev_warn(&pdev->dev, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
426 	ss->dev = &pdev->dev;
429 	spin_lock_init(&ss->slock);
442 	err = pm_runtime_resume_and_get(ss->dev);
446 	writel(SS_ENABLED, ss->base + SS_CTL);
447 	v = readl(ss->base + SS_CTL);
450 	dev_info(&pdev->dev, "Die ID %d\n", v);
451 	writel(0, ss->base + SS_CTL);
453 	pm_runtime_put_sync(ss->dev);
461 				dev_err(ss->dev, "Fail to register %s\n",
469 				dev_err(ss->dev, "Fail to register %s\n",
477 				dev_err(ss->dev, "Fail to register %s\n",
485 	ss->dbgfs_dir = debugfs_create_dir("sun4i-ss", NULL);
486 	ss->dbgfs_stats = debugfs_create_file("stats", 0444, ss->dbgfs_dir, ss,
491 	i--;
492 	for (; i >= 0; i--) {
533 	{ .compatible = "allwinner,sun4i-a10-crypto",
536 	{ .compatible = "allwinner,sun8i-a33-crypto",
547 		.name           = "sun4i-ss",
555 MODULE_ALIAS("platform:sun4i-ss");