drivers/clocksource/timer-npcm7xx.c

61 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
63 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
73 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
75 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
85 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
88 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
98 	writel(timer_of_period(to), timer_of_base(to) + NPCM7XX_REG_TICR0);
100 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
103 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
114 	writel(evt, timer_of_base(to) + NPCM7XX_REG_TICR0);
115 	val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
117 	writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
127 	writel(NPCM7XX_T0_CLR_INT, timer_of_base(to) + NPCM7XX_REG_TISR);
158 		timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0);
161 		timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TISR);
174 		timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
176 		timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TICR1);
178 	val = readl(timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
180 	writel(val, timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR1);
182 	clocksource_mmio_init(timer_of_base(&npcm7xx_to) +
216 		timer_of_base(&npcm7xx_to), timer_of_irq(&npcm7xx_to));