drivers/clocksource/timer-cadence-ttc.c

396 	struct ttc_timer_clockevent *ttcce = container_of(ttc,
404 		clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
417 	struct ttc_timer_clockevent *ttcce;
420 	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
421 	if (!ttcce)
424 	ttcce->ttc.clk = clk;
426 	err = clk_prepare_enable(ttcce->ttc.clk);
430 	ttcce->ttc.clk_rate_change_nb.notifier_call =
432 	ttcce->ttc.clk_rate_change_nb.next = NULL;
434 	err = clk_notifier_register(ttcce->ttc.clk,
435 				    &ttcce->ttc.clk_rate_change_nb);
441 	ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
443 	ttcce->ttc.base_addr = base;
444 	ttcce->ce.name = "ttc_clockevent";
445 	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
446 	ttcce->ce.set_next_event = ttc_set_next_event;
447 	ttcce->ce.set_state_shutdown = ttc_shutdown;
448 	ttcce->ce.set_state_periodic = ttc_set_periodic;
449 	ttcce->ce.set_state_oneshot = ttc_shutdown;
450 	ttcce->ce.tick_resume = ttc_resume;
451 	ttcce->ce.rating = 200;
452 	ttcce->ce.irq = irq;
453 	ttcce->ce.cpumask = cpu_possible_mask;
460 	writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
462 		     ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
463 	writel_relaxed(0x1,  ttcce->ttc.base_addr + TTC_IER_OFFSET);
466 			  IRQF_TIMER, ttcce->ce.name, ttcce);
470 	clockevents_config_and_register(&ttcce->ce,
471 			ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
476 	clk_disable_unprepare(ttcce->ttc.clk);
478 	kfree(ttcce);