Lines Matching refs:ch
84 static inline unsigned long sh_tmu_read(struct sh_tmu_channel *ch, int reg_nr) in sh_tmu_read() argument
89 switch (ch->tmu->model) { in sh_tmu_read()
91 return ioread8(ch->tmu->mapbase + 2); in sh_tmu_read()
93 return ioread8(ch->tmu->mapbase + 4); in sh_tmu_read()
100 return ioread16(ch->base + offs); in sh_tmu_read()
102 return ioread32(ch->base + offs); in sh_tmu_read()
105 static inline void sh_tmu_write(struct sh_tmu_channel *ch, int reg_nr, in sh_tmu_write() argument
111 switch (ch->tmu->model) { in sh_tmu_write()
113 return iowrite8(value, ch->tmu->mapbase + 2); in sh_tmu_write()
115 return iowrite8(value, ch->tmu->mapbase + 4); in sh_tmu_write()
122 iowrite16(value, ch->base + offs); in sh_tmu_write()
124 iowrite32(value, ch->base + offs); in sh_tmu_write()
127 static void sh_tmu_start_stop_ch(struct sh_tmu_channel *ch, int start) in sh_tmu_start_stop_ch() argument
132 raw_spin_lock_irqsave(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
133 value = sh_tmu_read(ch, TSTR); in sh_tmu_start_stop_ch()
136 value |= 1 << ch->index; in sh_tmu_start_stop_ch()
138 value &= ~(1 << ch->index); in sh_tmu_start_stop_ch()
140 sh_tmu_write(ch, TSTR, value); in sh_tmu_start_stop_ch()
141 raw_spin_unlock_irqrestore(&ch->tmu->lock, flags); in sh_tmu_start_stop_ch()
144 static int __sh_tmu_enable(struct sh_tmu_channel *ch) in __sh_tmu_enable() argument
147 sh_tmu_start_stop_ch(ch, 0); in __sh_tmu_enable()
150 sh_tmu_write(ch, TCOR, 0xffffffff); in __sh_tmu_enable()
151 sh_tmu_write(ch, TCNT, 0xffffffff); in __sh_tmu_enable()
154 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in __sh_tmu_enable()
157 sh_tmu_start_stop_ch(ch, 1); in __sh_tmu_enable()
162 static int sh_tmu_enable(struct sh_tmu_channel *ch) in sh_tmu_enable() argument
164 if (ch->enable_count++ > 0) in sh_tmu_enable()
167 dev_pm_syscore_device(&ch->tmu->pdev->dev, true); in sh_tmu_enable()
169 return __sh_tmu_enable(ch); in sh_tmu_enable()
172 static void __sh_tmu_disable(struct sh_tmu_channel *ch) in __sh_tmu_disable() argument
175 sh_tmu_start_stop_ch(ch, 0); in __sh_tmu_disable()
178 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in __sh_tmu_disable()
181 static void sh_tmu_disable(struct sh_tmu_channel *ch) in sh_tmu_disable() argument
183 if (WARN_ON(ch->enable_count == 0)) in sh_tmu_disable()
186 if (--ch->enable_count > 0) in sh_tmu_disable()
189 __sh_tmu_disable(ch); in sh_tmu_disable()
191 dev_pm_syscore_device(&ch->tmu->pdev->dev, false); in sh_tmu_disable()
194 static void sh_tmu_set_next(struct sh_tmu_channel *ch, unsigned long delta, in sh_tmu_set_next() argument
198 sh_tmu_start_stop_ch(ch, 0); in sh_tmu_set_next()
201 sh_tmu_read(ch, TCR); in sh_tmu_set_next()
204 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); in sh_tmu_set_next()
208 sh_tmu_write(ch, TCOR, delta); in sh_tmu_set_next()
210 sh_tmu_write(ch, TCOR, 0xffffffff); in sh_tmu_set_next()
212 sh_tmu_write(ch, TCNT, delta); in sh_tmu_set_next()
215 sh_tmu_start_stop_ch(ch, 1); in sh_tmu_set_next()
220 struct sh_tmu_channel *ch = dev_id; in sh_tmu_interrupt() local
223 if (clockevent_state_oneshot(&ch->ced)) in sh_tmu_interrupt()
224 sh_tmu_write(ch, TCR, TCR_TPSC_CLK4); in sh_tmu_interrupt()
226 sh_tmu_write(ch, TCR, TCR_UNIE | TCR_TPSC_CLK4); in sh_tmu_interrupt()
229 ch->ced.event_handler(&ch->ced); in sh_tmu_interrupt()
240 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_read() local
242 return sh_tmu_read(ch, TCNT) ^ 0xffffffff; in sh_tmu_clocksource_read()
247 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_enable() local
250 if (WARN_ON(ch->cs_enabled)) in sh_tmu_clocksource_enable()
253 ret = sh_tmu_enable(ch); in sh_tmu_clocksource_enable()
255 ch->cs_enabled = true; in sh_tmu_clocksource_enable()
262 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_disable() local
264 if (WARN_ON(!ch->cs_enabled)) in sh_tmu_clocksource_disable()
267 sh_tmu_disable(ch); in sh_tmu_clocksource_disable()
268 ch->cs_enabled = false; in sh_tmu_clocksource_disable()
273 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_suspend() local
275 if (!ch->cs_enabled) in sh_tmu_clocksource_suspend()
278 if (--ch->enable_count == 0) { in sh_tmu_clocksource_suspend()
279 __sh_tmu_disable(ch); in sh_tmu_clocksource_suspend()
280 dev_pm_genpd_suspend(&ch->tmu->pdev->dev); in sh_tmu_clocksource_suspend()
286 struct sh_tmu_channel *ch = cs_to_sh_tmu(cs); in sh_tmu_clocksource_resume() local
288 if (!ch->cs_enabled) in sh_tmu_clocksource_resume()
291 if (ch->enable_count++ == 0) { in sh_tmu_clocksource_resume()
292 dev_pm_genpd_resume(&ch->tmu->pdev->dev); in sh_tmu_clocksource_resume()
293 __sh_tmu_enable(ch); in sh_tmu_clocksource_resume()
297 static int sh_tmu_register_clocksource(struct sh_tmu_channel *ch, in sh_tmu_register_clocksource() argument
300 struct clocksource *cs = &ch->cs; in sh_tmu_register_clocksource()
312 dev_info(&ch->tmu->pdev->dev, "ch%u: used as clock source\n", in sh_tmu_register_clocksource()
313 ch->index); in sh_tmu_register_clocksource()
315 clocksource_register_hz(cs, ch->tmu->rate); in sh_tmu_register_clocksource()
324 static void sh_tmu_clock_event_start(struct sh_tmu_channel *ch, int periodic) in sh_tmu_clock_event_start() argument
326 sh_tmu_enable(ch); in sh_tmu_clock_event_start()
329 ch->periodic = (ch->tmu->rate + HZ/2) / HZ; in sh_tmu_clock_event_start()
330 sh_tmu_set_next(ch, ch->periodic, 1); in sh_tmu_clock_event_start()
336 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); in sh_tmu_clock_event_shutdown() local
339 sh_tmu_disable(ch); in sh_tmu_clock_event_shutdown()
346 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); in sh_tmu_clock_event_set_state() local
350 sh_tmu_disable(ch); in sh_tmu_clock_event_set_state()
352 dev_info(&ch->tmu->pdev->dev, "ch%u: used for %s clock events\n", in sh_tmu_clock_event_set_state()
353 ch->index, periodic ? "periodic" : "oneshot"); in sh_tmu_clock_event_set_state()
354 sh_tmu_clock_event_start(ch, periodic); in sh_tmu_clock_event_set_state()
371 struct sh_tmu_channel *ch = ced_to_sh_tmu(ced); in sh_tmu_clock_event_next() local
376 sh_tmu_set_next(ch, delta, 0); in sh_tmu_clock_event_next()
390 static void sh_tmu_register_clockevent(struct sh_tmu_channel *ch, in sh_tmu_register_clockevent() argument
393 struct clock_event_device *ced = &ch->ced; in sh_tmu_register_clockevent()
408 dev_info(&ch->tmu->pdev->dev, "ch%u: used for clock events\n", in sh_tmu_register_clockevent()
409 ch->index); in sh_tmu_register_clockevent()
411 clockevents_config_and_register(ced, ch->tmu->rate, 0x300, 0xffffffff); in sh_tmu_register_clockevent()
413 ret = request_irq(ch->irq, sh_tmu_interrupt, in sh_tmu_register_clockevent()
415 dev_name(&ch->tmu->pdev->dev), ch); in sh_tmu_register_clockevent()
417 dev_err(&ch->tmu->pdev->dev, "ch%u: failed to request irq %d\n", in sh_tmu_register_clockevent()
418 ch->index, ch->irq); in sh_tmu_register_clockevent()
423 static int sh_tmu_register(struct sh_tmu_channel *ch, const char *name, in sh_tmu_register() argument
427 ch->tmu->has_clockevent = true; in sh_tmu_register()
428 sh_tmu_register_clockevent(ch, name); in sh_tmu_register()
430 ch->tmu->has_clocksource = true; in sh_tmu_register()
431 sh_tmu_register_clocksource(ch, name); in sh_tmu_register()
437 static int sh_tmu_channel_setup(struct sh_tmu_channel *ch, unsigned int index, in sh_tmu_channel_setup() argument
445 ch->tmu = tmu; in sh_tmu_channel_setup()
446 ch->index = index; in sh_tmu_channel_setup()
449 ch->base = tmu->mapbase + 4 + ch->index * 12; in sh_tmu_channel_setup()
451 ch->base = tmu->mapbase + 8 + ch->index * 12; in sh_tmu_channel_setup()
453 ch->irq = platform_get_irq(tmu->pdev, index); in sh_tmu_channel_setup()
454 if (ch->irq < 0) in sh_tmu_channel_setup()
455 return ch->irq; in sh_tmu_channel_setup()
457 ch->cs_enabled = false; in sh_tmu_channel_setup()
458 ch->enable_count = 0; in sh_tmu_channel_setup()
460 return sh_tmu_register(ch, dev_name(&tmu->pdev->dev), in sh_tmu_channel_setup()