1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2016-17 Synopsys, Inc. (www.synopsys.com)
4  * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
11  * ARCv2 based HS38 cores have RTC (in-core) and GFRC (inside ARConnect/MCIP)
18 #include <linux/clk-provider.h>
26 #include <soc/arc/timers.h>
27 #include <soc/arc/mcip.h>
39 		pr_err("timer missing clk\n");  in arc_get_timer_clk()
65 	 * MCIP_CMD/MCIP_READBACK however micro-architecturally there's  in arc_read_gfrc()
66 	 * an instance PER ARC CORE (not per cluster), and there are dedicated  in arc_read_gfrc()
70 	 * trying to access two different sub-components (like GFRC,  in arc_read_gfrc()
71 	 * inter-core interrupt, etc...). HW also supports simultaneously  in arc_read_gfrc()
75 	 * defined in arch/arc/kernel/mcip.c  in arc_read_gfrc()
110 		pr_warn("Global-64-bit-Ctr clocksource not detected\n");  in arc_cs_setup_gfrc()
111 		return -ENXIO;  in arc_cs_setup_gfrc()
122 TIMER_OF_DECLARE(arc_gfrc, "snps,archs-timer-gfrc", arc_cs_setup_gfrc);
136 	 *  - interrupt/exception taken between the two reads  in arc_read_rtc()
137 	 *  - high increments after low has been read  in arc_read_rtc()
163 	struct bcr_timer timer;  in arc_cs_setup_rtc()  local
166 	READ_BCR(ARC_REG_TIMERS_BCR, timer);  in arc_cs_setup_rtc()
167 	if (!timer.rtc) {  in arc_cs_setup_rtc()
168 		pr_warn("Local-64-bit-Ctr clocksource not detected\n");  in arc_cs_setup_rtc()
169 		return -ENXIO;  in arc_cs_setup_rtc()
174 		pr_warn("Local-64-bit-Ctr not usable in SMP\n");  in arc_cs_setup_rtc()
175 		return -EINVAL;  in arc_cs_setup_rtc()
188 TIMER_OF_DECLARE(arc_rtc, "snps,archs-timer-rtc", arc_cs_setup_rtc);
207 	.name   = "ARC Timer1",
220 		return -EINVAL;  in arc_cs_setup_timer1()
240  * Arm the timer to interrupt after @cycles
262 	 * At X Hz, 1 sec = 1000ms -> X cycles;  in arc_clkevent_set_periodic()
263 	 *		      10ms -> X / 100 cycles  in arc_clkevent_set_periodic()
270 	.name			= "ARC Timer0",
289 	 *    - For ARC700, any write to CTRL reg ACKs it, so just rewrite  in timer_irq_handler()
291 	 *    - For HS3x, it is a bit subtle. On taken count-down interrupt,  in timer_irq_handler()
295 	 * 2. Re-arm interrupt if periodic by writing to IE bit [0]  in timer_irq_handler()
299 	evt->event_handler(evt);  in timer_irq_handler()
309 	evt->cpumask = cpumask_of(smp_processor_id());  in arc_timer_starting_cpu()
333 		return -EINVAL;  in arc_clockevent_setup()
342 				 "Timer0 (per-cpu-tick)", evt);  in arc_clockevent_setup()
349 				"clockevents/arc/timer:starting",  in arc_clockevent_setup()
373 TIMER_OF_DECLARE(arc_clkevt, "snps,arc-timer", arc_of_timer_init);