clk/xilinx/clk-xlnx-clock-wizard.c

125  * struct clk_wzrd - Clock wizard private data structure
136 struct clk_wzrd {
148  * struct clk_wzrd_divider - clock divider specific to clk_wzrd
155  * @flags:	clk_wzrd divider flags
184 #define to_clk_wzrd(_nb) container_of(_nb, struct clk_wzrd, nb)
193 /* spin lock variable for clk_wzrd */
925 	struct clk_wzrd *clk_wzrd = to_clk_wzrd(nb);
927 	if (clk_wzrd->suspended)
930 	if (ndata->clk == clk_wzrd->clk_in1)
931 		max = clk_wzrd_max_freq[clk_wzrd->speed_grade - 1];
932 	else if (ndata->clk == clk_wzrd->axi_clk)
951 	struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
953 	clk_disable_unprepare(clk_wzrd->axi_clk);
954 	clk_wzrd->suspended = true;
962 	struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
964 	ret = clk_prepare_enable(clk_wzrd->axi_clk);
970 	clk_wzrd->suspended = false;
985 	struct clk_wzrd *clk_wzrd = dev_get_drvdata(dev);
1004 			clk_wzrd->clk_data.hws[0] = clk_wzrd_ver_register_divider
1006 				__clk_get_name(clk_wzrd->clk_in1), 0,
1007 				clk_wzrd->base, WZRD_CLK_CFG_REG(is_versal, 3),
1016 		edge = !!(readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0)) &
1018 		regl = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 1)) &
1020 		regh = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 1)) &
1027 		regl = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 51)) &
1030 			regl = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 48)) &
1037 			clk_wzrd->clk_data.hws[0] = clk_wzrd_register_divider
1039 				__clk_get_name(clk_wzrd->clk_in1), 0,
1040 				clk_wzrd->base, WZRD_CLK_CFG_REG(is_versal, 3),
1048 		reg = readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0));
1060 	clk_wzrd->clks_internal[wzrd_clk_mul] = devm_clk_hw_register_fixed_factor
1062 			 __clk_get_name(clk_wzrd->clk_in1),
1064 	if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul])) {
1066 		return PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul]);
1074 		edged = !!(readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 20)) &
1076 		regld = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 21)) &
1078 		reghd = (readl(clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 21)) &
1084 		clk_mul_name = clk_hw_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]);
1085 		clk_wzrd->clks_internal[wzrd_clk_mul_div] =
1088 		ctrl_reg = clk_wzrd->base + WZRD_CLK_CFG_REG(is_versal, 0);
1089 		clk_wzrd->clks_internal[wzrd_clk_mul_div] = devm_clk_hw_register_divider
1091 			 clk_hw_get_name(clk_wzrd->clks_internal[wzrd_clk_mul]),
1095 	if (IS_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div])) {
1097 		return PTR_ERR(clk_wzrd->clks_internal[wzrd_clk_mul_div]);
1107 			clk_wzrd->clk_data.hws[i] = clk_wzrd_ver_register_divider
1110 						 clk_wzrd->base,
1119 				clk_wzrd->clk_data.hws[i] = clk_wzrd_register_divf
1120 					(dev, clkout_name, clk_name, flags, clk_wzrd->base,
1127 				clk_wzrd->clk_data.hws[i] = clk_wzrd_register_divider
1128 					(dev, clkout_name, clk_name, 0, clk_wzrd->base,
1135 		if (IS_ERR(clk_wzrd->clk_data.hws[i])) {
1137 			return PTR_ERR(clk_wzrd->clk_data.hws[i]);
1147 	struct clk_wzrd *clk_wzrd;
1156 	clk_wzrd = devm_kzalloc(&pdev->dev, struct_size(clk_wzrd, clk_data.hws, nr_outputs),
1158 	if (!clk_wzrd)
1160 	platform_set_drvdata(pdev, clk_wzrd);
1162 	clk_wzrd->base = devm_platform_ioremap_resource(pdev, 0);
1163 	if (IS_ERR(clk_wzrd->base))
1164 		return PTR_ERR(clk_wzrd->base);
1166 	clk_wzrd->axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
1167 	if (IS_ERR(clk_wzrd->axi_clk))
1168 		return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk),
1170 	rate = clk_get_rate(clk_wzrd->axi_clk);
1177 		ret = of_property_read_u32(np, "xlnx,speed-grade", &clk_wzrd->speed_grade);
1179 			if (clk_wzrd->speed_grade < 1 || clk_wzrd->speed_grade > 3) {
1181 					 clk_wzrd->speed_grade);
1182 				clk_wzrd->speed_grade = 0;
1186 		clk_wzrd->clk_in1 = devm_clk_get(&pdev->dev, "clk_in1");
1187 		if (IS_ERR(clk_wzrd->clk_in1))
1188 			return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->clk_in1),
1195 		clk_wzrd->clk_data.num = nr_outputs;
1197 						  &clk_wzrd->clk_data);
1203 		if (clk_wzrd->speed_grade) {
1204 			clk_wzrd->nb.notifier_call = clk_wzrd_clk_notifier;
1206 			ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->clk_in1,
1207 							 &clk_wzrd->nb);
1212 			ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->axi_clk,
1213 							 &clk_wzrd->nb);