clk/xilinx/clk-xlnx-clock-wizard.c

130  * @axi_clk:		Handle to input clock 's_axi_aclk'
140 	struct clk *axi_clk;
932 	else if (ndata->clk == clk_wzrd->axi_clk)
953 	clk_disable_unprepare(clk_wzrd->axi_clk);
964 	ret = clk_prepare_enable(clk_wzrd->axi_clk);
1166 	clk_wzrd->axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
1167 	if (IS_ERR(clk_wzrd->axi_clk))
1168 		return dev_err_probe(&pdev->dev, PTR_ERR(clk_wzrd->axi_clk),
1170 	rate = clk_get_rate(clk_wzrd->axi_clk);
1212 			ret = devm_clk_notifier_register(&pdev->dev, clk_wzrd->axi_clk,