clk/ti/dpll3xxx.c

54 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
57 	ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
73 	while (((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask)
151 	if ((ti_clk_ll_ops->clk_readl(&dd->idlest_reg) & dd->idlest_mask) ==
308 	ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
334 		v = ti_clk_ll_ops->clk_readl(&dd->ssc_modfreq_reg);
338 		ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg);
364 		v = ti_clk_ll_ops->clk_readl(&dd->ssc_deltam_reg);
368 		ti_clk_ll_ops->clk_writel(v, &dd->ssc_deltam_reg);
373 	ti_clk_ll_ops->clk_writel(ctrl, &dd->control_reg);
399 		v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
402 		ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
406 	v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
452 	ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
456 		v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
472 		ti_clk_ll_ops->clk_writel(v, &dd->control_reg);
534 		r = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
570 		ti_clk_ll_ops->clkdm_clk_disable(clk->clkdm, hw->clk);
741 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
775 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
778 	ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
800 	v = ti_clk_ll_ops->clk_readl(&dd->autoidle_reg);
803 	ti_clk_ll_ops->clk_writel(v, &dd->autoidle_reg);
860 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg) & dd->enable_mask;
884 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
888 		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
917 		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
921 		ti_clk_ll_ops->clk_writel(v, &dd->mult_div1_reg);
945 	v = ti_clk_ll_ops->clk_readl(&dd->control_reg);
949 		v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);
974 	ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg);
975 	mult_div1 = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg);