Lines Matching refs:tegra30_cpu_clk_sctx

147 } tegra30_cpu_clk_sctx;
1123 	tegra30_cpu_clk_sctx.clk_csite_src =
1127 	tegra30_cpu_clk_sctx.cpu_burst =
1129 	tegra30_cpu_clk_sctx.pllx_base =
1131 	tegra30_cpu_clk_sctx.pllx_misc =
1133 	tegra30_cpu_clk_sctx.cclk_divider =
1157 		if (misc != tegra30_cpu_clk_sctx.pllx_misc ||
1158 		    base != tegra30_cpu_clk_sctx.pllx_base) {
1160 			writel(tegra30_cpu_clk_sctx.pllx_misc,
1162 			writel(tegra30_cpu_clk_sctx.pllx_base,
1166 			if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1175 	writel(tegra30_cpu_clk_sctx.cclk_divider,
1177 	writel(tegra30_cpu_clk_sctx.cpu_burst,
1180 	writel(tegra30_cpu_clk_sctx.clk_csite_src,