160 	struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);  in sg2042_clk_divider_recalc_rate()  local
164 	if (!(readl(divider->reg) & BIT(SHIFT_DIV_FACTOR_SEL))) {  in sg2042_clk_divider_recalc_rate()
165 		val = divider->initval;  in sg2042_clk_divider_recalc_rate()
167 		val = readl(divider->reg) >> divider->shift;  in sg2042_clk_divider_recalc_rate()
168 		val &= clk_div_mask(divider->width);  in sg2042_clk_divider_recalc_rate()
172 				       divider->div_flags, divider->width);  in sg2042_clk_divider_recalc_rate()
182 	struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);  in sg2042_clk_divider_determine_rate()  local
187 	if (divider->div_flags & CLK_DIVIDER_READ_ONLY) {  in sg2042_clk_divider_determine_rate()
188 		if (!(readl(divider->reg) & BIT(SHIFT_DIV_FACTOR_SEL))) {  in sg2042_clk_divider_determine_rate()
189 			bestdiv = divider->initval;  in sg2042_clk_divider_determine_rate()
191 			bestdiv = readl(divider->reg) >> divider->shift;  in sg2042_clk_divider_determine_rate()
192 			bestdiv &= clk_div_mask(divider->width);  in sg2042_clk_divider_determine_rate()
197 					      divider->width, divider->div_flags);  in sg2042_clk_divider_determine_rate()
211 	struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);  in sg2042_clk_divider_set_rate()  local
216 				divider->width, divider->div_flags);  in sg2042_clk_divider_set_rate()
218 	if (divider->lock)  in sg2042_clk_divider_set_rate()
219 		spin_lock_irqsave(divider->lock, flags);  in sg2042_clk_divider_set_rate()
221 		__acquire(divider->lock);  in sg2042_clk_divider_set_rate()
229 	val = readl(divider->reg);  in sg2042_clk_divider_set_rate()
233 	writel(val, divider->reg);  in sg2042_clk_divider_set_rate()
235 	if (divider->div_flags & CLK_DIVIDER_HIWORD_MASK) {  in sg2042_clk_divider_set_rate()
236 		val = clk_div_mask(divider->width) << (divider->shift + 16);  in sg2042_clk_divider_set_rate()
238 		val = readl(divider->reg);  in sg2042_clk_divider_set_rate()
239 		val &= ~(clk_div_mask(divider->width) << divider->shift);  in sg2042_clk_divider_set_rate()
241 	val |= value << divider->shift;  in sg2042_clk_divider_set_rate()
243 	writel(val, divider->reg);  in sg2042_clk_divider_set_rate()
248 	writel(val, divider->reg);  in sg2042_clk_divider_set_rate()
250 	if (divider->lock)  in sg2042_clk_divider_set_rate()
251 		spin_unlock_irqrestore(divider->lock, flags);  in sg2042_clk_divider_set_rate()
253 		__release(divider->lock);  in sg2042_clk_divider_set_rate()